Electrically-programmable integrated circuit antifuses

Details Electrically-programmable integrated circuit antifuses Electrically-programmable integrated circuit antifuses

2005-05-24

2005-05-24

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Passive components in ics

C257S529000, C257S603000, C257S106000, C257S175000, C438S131000, C438S467000, C438S600000, C438S983000

Reexamination Certificate

active

06897543

ABSTRACT:
Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) antifuse transistor serves as an electrically-programmable antifuse. In its unprogrammed state, the antifuse transistor is off and has a relatively high resistance. During programming, the antifuse transistor is turned on which melts the underlying silicon and causes a permanent reduction in the transistor's resistance. A sensing circuit monitors the resistance of the antifuse transistor and supplies a high or low output signal accordingly. The antifuse transistor may be turned on during programming by raising the voltage at its substrate relative to its source. The substrate may be connected to ground through a resistor. The substrate may be biased by causing current to flow through the resistor. Current may be made to flow through the resistor by inducing avalanche breakdown of the drain-substrate junction or by producing Zener breakdown of external Zener diode circuitry connected to the resistor.

REFERENCES:
patent: 4207556 (1980-06-01), Yoshi et al.
patent: 4433331 (1984-02-01), Kollaritsch
patent: 4609986 (1986-09-01), Hartmann et al.
patent: 4617479 (1986-10-01), Hartmann et al.
patent: 4642487 (1987-02-01), Carter
patent: 4761768 (1988-08-01), Turner et al.
patent: 5070384 (1991-12-01), McCollum et al.
patent: 5291434 (1994-03-01), Kowalski
patent: 5303199 (1994-04-01), Ishihara et al.
patent: 5463244 (1995-10-01), De Araujo et al.
patent: 5510730 (1996-04-01), El Gamal et al.
patent: 5774011 (1998-06-01), Au et al.
patent: 5831923 (1998-11-01), Casper
patent: 5844298 (1998-12-01), Smith et al.
patent: 6108261 (2000-08-01), Kim et al.
patent: 6125069 (2000-09-01), Aoki
patent: 6240033 (2001-05-01), Yang et al.
patent: 6456546 (2002-09-01), Kim et al.
patent: 6477094 (2002-11-01), Kim et al.
patent: 6674667 (2004-01-01), Forbes
patent: 20040100849 (2004-05-01), Novosel et al.
U.S. Appl. No. 10/780,427, Chih-Ching Shih et al.
Wei Zhange et al., “Energy Effect of the Laser-Induced Vertical Metallic Link”, IEEE Transactions on Semiconductor Manufacturing, vol. 14, No. 2, May 2001 pp 163-169.
“Analyzing the process window for laser copper-link processing” Solid State Technology—Semiconductor manufactoring and water fabrication, Jan. 8, 2003.
Alexander Kalnitsky et al. “CoSi2 integrated fuses on poly silicon for low voltage 0.18 um CMOS applications” (c) 1999 IEEE.
Mohsen Alavi “A PROM Element Based on Salicide Agglomeration of Poly Fuses in a CMOS logic process” IEEE International Electron Devices Meeting, Dec. 1997.
Noriaki Sato et al. “A New Programmable Cell Utilizing Insulator Breakdown”, IEDM 1985, pp 639-642.
Jinbong Kim et al. “Three-Transistor One-Time Programmable (OTP) ROM Cell Array Using Standard CMOS Gate Oxide Antifuse”, IEEE Electron Device Letters, vol. 24, No. 9, Sep. 2003 pp. 589-591.
Wei Zhang et al. “Laser-Formed Vertical Metallic Link and Potential Implementation in Digital Logic Integration”, PROC MAPLD, MD, 1999 pp 1-7 (B5).
V. Klee et al. “A 0.13 um logic-based embedded DRAM technology with electrical fuses, Cu interconnect in SiLK, sub-7ns random access time and its extension to the 0.10 um generation,” IEEE (c) 2001 IEDM (International Electron Devices Meeting), Technical Digest, pp 18.5.1-18.5.4.
Wei Zhang et al., “Reliability of laser-induced metallic vertical links,” IEEE Trans. on Advanced Packaging, pp 614-19 Nov. 1999 vol. 22 Issue 4.
JB Bernstein et al. “Analysis of laser metal-cut energy process window” IEEE Trans. on Semicond. Manuf., pp 228-234, May 2000, vol. 13, Issue 2.
JB Bernstein et al. “Laser energy limitation for buried metal cuts” IEEE Electron Device Letters, pp 4-6, Jan. 1998, vol. 19, Issue 1.
RT Smith et al. “Laser programmable redundancy and yield improvement in a 64 K DRAM”, IEEE Journal of Solid-State Circuits, pp 506-514 Oct. 1981, vol. 16, Issue 5.

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