Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Fusible link or intentional destruct circuit
Reexamination Certificate
2000-07-21
2002-05-21
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Fusible link or intentional destruct circuit
C327S534000
Reexamination Certificate
active
06392468
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention is related to integrated circuits and more particularly electrically programmable fuse devices.
2. Description of Related Art
A fuse device used on an integrated circuit is for the purpose of repairing a defect or selecting a functional option. The operation of using a fuse has required the use of a laser to vaporize a thin piece of poly-silicon that made up the fuse. This requires the fuse to be opened by the laser before final packaging of the semiconductor, and once the fuse is opened there is no recovery to the original state. With this limitation there has been a push to find ways to avoid the limitations of a fuse requiring a laser to break the connection.
In U.S. Pat. No. 5,642,316 (Tran et al.) a source follower EEPROM memory fuse is used to program memory redundancy circuits for repair of defective memory rows. The redundant memory circuits are initially outside the normal memory address range and through the use of fuses are brought into the normal memory address range to replace defective memory bits. This EEPROM fuse can be reused many times. In U.S. Pat. No. 5,258,947 (Sourgen) EEPROM cells are used in a regular memory state and can be programmed to perform the function of a fuse. The fuse function results from the breakdown of the tunnel oxide and places the memory cell into an irreversible state. In U.S. Pat. No. 5,233,566 (Imamiya et al.) a floating-gate, avalanche injected, MOS transistor (FAMOS) memory cell is connected in series with a fuse to provide a redundant memory cell. In U.S. Pat. No. 4,852,044 (Turner et al.) is described a security fuse device for a programmed logic device (PLD) that uses charge stored on a floating gate of a transistor to prevent access to the PLD architectural data.
In reference to “silicon Processing for the VLSI Era” by Stanley Wolf Ph. D., Lattice Press 1990, pp 624-625, a floating-gate avalanche-injection MOS transistor (FAMOS) device is describe din which charge is injected into a gate from hot electrons produced by avalanche breakdown of the drain-substrate pn junction. Once the electrons are transferred to the gate they are trapped there because of the potential energy barrier at the oxide-silicon interface.
A fuse like device that can be programmed to be on or off after packaging and hold its switching state for years can be a very useful tool. Not only can it be used for the classical repair of memories but it can also be used to activate or deactivate function and features of a particular circuit. These functions and features being changed at the command of the user provides additional flexibility without requiring factory intervention. Also being able to reverse a decision to chose a function can be very valuable particularly when problems arise.
SUMMARY OF THE INVENTION
This invention is an electronic fuse like device that is made up of two semiconductor devices connected by a floating gate. In a first embodiment a first of the two transistors is a P-channel device seated in an N-well on a P-substrate that provides the activation and de-activation of the electronic fuse. A second transistor connected to the floating gate is an N-channel transistor which is on or off depending upon the charge on the floating gate and provides a fuse like function.
Charge is programmed onto the floating gate by means of hot electrons or Fowler-Nordheim tunneling in the first transistor to enable the second transistor to be on and act as a non-blown fuse. Charge is remove from the floating gate using Fowler-Nordheim tunneling, turning off the second transistor, and enabling the second transistor to act as an open fuse.
In a second embodiment of this invention, a heavily doped P+ region is implanted around one end of a floating gate in an N well residing on a P substrate. At the other end of the floating gate is an N-channel transistor in the P-substrate. The heavily doped P+ region provides the means for programming charge onto the floating gate using either Fowler-Nordheim tunneling or hot electrons, and the N-channel transistor is either on or off depending upon the charge on the floating gate. Charge is removed form the floating gate using Fowler-Nordheim tunneling.
In a variation of the second embodiment of this invention, an N+ device formed by a heavily doped N+ region is implanted around one end of a floating gate in a P well residing in an N well on a P substrate. The other end of the floating gate is an N-channel transistor in the P well residing in an N well on the P substrate. The N+ device provides the means for programming charge onto the floating gate using either hot electrons or Fowler-Nordheim tunneling, and the N-channel transistor is either on or off depending upon the charge on the floating gate. Charge is removed from the floating gate using Fowler-Nordheim tunneling.
REFERENCES:
patent: 5465231 (1995-11-01), Ohsaki
patent: 5719427 (1998-02-01), Tong et al.
patent: 5898614 (1999-04-01), Takeuchi
patent: 5912937 (1999-06-01), Goetting et al.
patent: 6100560 (2000-08-01), Lovett
Ackerman Stephen B.
Saile George O.
Vanguard International Semiconductor Corporation
Zweizig Jeffrey
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