Electrically programmable fuse

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections

Reexamination Certificate

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Details

C257S529000, C257SE21592, C257SE23149

Reexamination Certificate

active

07960760

ABSTRACT:
A semiconductor device includes a fin-fuse and an SOI transistor. The SOI transistor is located on an SOI substrate and has a source region and a drain region. The fin-fuse is connected to one of the source/drain regions and has a fusible link located on the SOI substrate. The fusible link has a homogeneous dopant concentration.

REFERENCES:
patent: 6933591 (2005-08-01), Sidhu et al.
patent: 7067359 (2006-06-01), Wu
patent: 2002/0197781 (2002-12-01), Bryant et al.
patent: 2003/0193058 (2003-10-01), Fried et al.
patent: 2005/0173740 (2005-08-01), Jin
Xuejue Huang, et al., “Sub-50 nm P-Channel FinFET” IEEE Transactions on Electron Devices, vol. 48, No. 5, pp. 880-886, May 2001.

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