Electrically programmable floating gate semiconductor memory dev

Details Electrically programmable floating gate semiconductor memory dev Electrically programmable floating gate semiconductor memory dev

1984-04-26

1985-05-07

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 29576B, 148 15, H01L 21265, H01L 2976

Patent

active

045148970

ABSTRACT:
An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates positioned beneath control gates formed by row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate; the floating gate is charged through an insulator between the floating gate and the channel. A simplified process for fabrication of the devices eliminates photoresist and implant steps yet produces improved characteristics in the form of higher gain and lower body effect.

REFERENCES:
patent: 4208780 (1980-06-01), Richman
patent: 4214359 (1980-07-01), Kahng
patent: 4222063 (1980-09-01), Rogers
patent: 4282646 (1981-08-01), Fortino et al.
patent: 4317273 (1982-03-01), Guterman et al.
patent: 4376947 (1983-03-01), Chiu et al.
Sai-Halasz et al., "Simple Realization of an Edge-Doped FET", IBM Techn. Discl. Bull., vol. 26, No. 6, Nov. 1983.

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