Electrically programmable floating gate semiconductor memory dev

Details Electrically programmable floating gate semiconductor memory dev Electrically programmable floating gate semiconductor memory dev

1979-09-04

1983-03-15

Larkins, William D.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 89, 365185, H01L 2978, G11C 1140

Patent

active

043769470

ABSTRACT:
An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates positioned beneath control gates formed by row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate; the floating gate is charged through an insulator between the floating gate and the channel. A simplified process for fabrication of the devices eliminates photoresist and implant steps yet produces improved characteristics in the form of higher gain and lower body effect.

REFERENCES:
patent: 3868187 (1975-02-01), Masuoka
patent: 4122544 (1978-10-01), McElroy
patent: 4151021 (1979-04-01), McElroy
patent: 4161039 (1979-07-01), Roessler
patent: 4199996 (1978-10-01), Jhabvala
patent: 4222063 (1980-09-01), Rodgers
patent: 4258378 (1981-03-01), Wall
patent: 4302766 (1981-11-01), Guterman et al.
patent: 4317273 (1982-03-01), Guterman et al.

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