Electrically programmable anti-fuse circuit

Details Electrically programmable anti-fuse circuit Electrically programmable anti-fuse circuit

1997-09-26

2000-02-01

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Fusible link or intentional destruct circuit

327526, H01H 3776

Patent

active

060207779

ABSTRACT:
An array of anti-fuse cells forming rows and columns of a matrix is described. The anti-fuse cell includes an MOS capacitor connected to a source of high voltage which is capable of rendering the capacitor permanently conductive. A first voltage limiting transistor connects the free end of the MOS capacitor to a second transistor. An address decoder provides address signals to a source and gate of the second transistor within the cell. The MOS capacitor is rendered permanently conductive when the first and second transistors are rendered conductive. The high voltage is confined to the MOS capacitor, which is fused through the high current being drawn through the capacitor by the first and second transistors. Other components on the integrated circuit carrying the array of fusible cells are maintained free of any high voltage.

REFERENCES:
patent: 4507757 (1985-03-01), McElroy
patent: 4899205 (1990-02-01), Hamdy et al.
patent: 5291434 (1994-03-01), Kowalski
patent: 5334880 (1994-08-01), Abadeer et al.
patent: 5401993 (1995-03-01), Yamauchi et al.
patent: 5689455 (1997-11-01), Mullarkey et al.
patent: 5724282 (1998-03-01), Loughmiller et al.
patent: 5847987 (1998-12-01), Cutter et al.

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