Static information storage and retrieval – Floating gate – Particular biasing
Patent
1996-06-11
1998-04-28
Nelms, David C.
Static information storage and retrieval
Floating gate
Particular biasing
365218, 36518524, G11C 700
Patent
active
057454175
ABSTRACT:
In erasing, electrons are simultaneously injected into floating gates from sources of a plurality of memory cells. Thus, the threshold voltages of the plurality of memory cells are increased. In programming, electrons are emitted from a floating gate of a selected memory cell to a drain. Thus, the threshold voltage of the selected memory cell is reduced.
REFERENCES:
patent: 4173791 (1979-11-01), Bell
patent: 4377857 (1983-03-01), Tickle
patent: 4451905 (1984-05-01), Moyer
patent: 4868619 (1989-09-01), Mukherjee et al.
patent: 4878199 (1989-10-01), Mizutani et al.
patent: 4887238 (1989-12-01), Terasawa et al.
patent: 4959812 (1990-09-01), Monodomi et al.
patent: 5022000 (1991-06-01), Terasawa et al.
patent: 5077691 (1991-12-01), Haddad et al.
patent: 5084843 (1992-01-01), Mitsuishi et al.
patent: 5088060 (1992-02-01), Endoh et al.
patent: 5126808 (1992-06-01), Montalvo et al.
patent: 5197027 (1993-03-01), Challa
patent: 5278439 (1994-01-01), Ma et al.
"Experimental 4-Mb Flash EEPROM with Sector Erase", IEEE Journal of Solid-State Circuits, Mike McConnell, et al., vol. 26, No. 4, Apr. 1991, pp. 484-491.
"A High-Density NAND EEPROM with Block-Page Programming for Microcomputer Applications", IEEE Journal of Solid-State Circuits, Yoshihisa Iwata, et al., vol. 25, No. 2, Apr. 1990, pp. 417-424.
"A 4-Mbit NAND-EEPROM with Tight Programmed Vt Distribution", Tanaka et al., 1990 Symposium on VLSI Circuits Digest of Technical Papers, pp. 105-106.
"A New Erasing and Row Decoding Scheme for Low Supply Voltage Operation 16 Mb/64-Mb Flash Memories", Miyawaki et al., IEEE Journal of Solid-State Circuits, vol. 27, No. 4, Apr. 1992, pp. 583-5887.
"An Experimental 4-Mbit CMOS EEPROM with a NAND-Structured Cell", Momodomi et al., IEEE Journal of Solid-State Circuits, Vo. 24, No. 5., Oct. 1989, pp. 1238-1241.
"An In-System Reprogrammable 32KX8 CMOS Flash Memory", Kynett et al., IEEE Journal of Solid-State Circuits, vol. 23, Nov. 5, Oct. 1988, pp. 1157-1163.
Nikkei Electronics, Feb. 17, 1992 (No. 547), pp. 180-181.
"A 3.42 .mu.m2Flash Memory Cell Technology Conformable to a Sector Erase", Kume et al., 1991 Symposium on VLSI Technology, pp. 77-78.
"A 4-MB NAND EEPROM with Tight Programmed Vt Distribution", Momoodomi et al., IEEE Journal of Solid-State Circuits, vol. 26, No.4, Apr. 1991, pp. 492-495.
"A 5V Only 16Mbit Flash EEPROM Cell Using Highly Reliable Write/Erase Technologies", Kodama, et al., 1991 Symposium on VLSI Technology, pp. 75-76.
"An Asymmetrical Lightly Doped Source Cell for Vitural Ground High-Density EPROM's", Yoshikawa et al., IEEE Transactions on Electron Devices, vol.37, No. 4, Apr. 1990, pp. 1046-1051.
Jacob Millman, Ph.D. et al., Microelectronics Second Edition, McGraw Hill Book Company, 1987, pp. 191-193.
Ajika Natsuo
Fukumoto Atsushi
Futatsuya Tomoshi
Kobayashi Shin-ichi
Kunori Yuichi
Le Vu A.
Mitsubishi Denki & Kabushiki Kaisha
Nelms David C.
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