Electrically programmable and erasable nonvolatile semiconductor

Static information storage and retrieval – Floating gate – Particular biasing

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

36518513, 36518533, G11C 1140

Patent

active

056595050

ABSTRACT:
In erasing, electrons are simultaneously injected into floating gates from sources of a plurality of memory cells. Thus, the threshold voltages of the plurality of memory cells are increased. In programming, electrons are emitted from a floating gate of a selected memory cell to a drain. Thus, the threshold voltage of the selected memory cell is reduced.

REFERENCES:
patent: 4377857 (1983-03-01), Tickle
patent: 4460982 (1984-07-01), Gee et al.
patent: 4868619 (1989-09-01), Mukherjee et al.
patent: 4878199 (1989-10-01), Mizutani et al.
patent: 4887238 (1989-12-01), Terasawa et al.
patent: 4959812 (1990-09-01), Monodomi et al.
patent: 5022000 (1991-06-01), Terasawa et al.
patent: 5077691 (1991-12-01), Haddad et al.
patent: 5088060 (1992-02-01), Endoh et al.
patent: 5126808 (1992-06-01), Montalvo et al.
patent: 5245570 (1993-09-01), Fazio et al.
patent: 5278439 (1994-01-01), Ma et al.
patent: 5341342 (1994-08-01), Brahmbhatt
patent: 5365484 (1994-11-01), Cleveland et al.
"A 4-Mbit NAND-EEPROM with Tight Programmed Vt Distribution", Tomoharu Tanaka et al., 1990 Symposium on VLSI Circuits Digest of Technical Papers, pp. 105-106.
"An Experimental 4-Mbit CMOS EEPROM with a NAND-Structured Cell", Masaki Momodomi, et al., IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1238-1241.
"A New Erasing and Row Decoding Scheme for Low Supply Voltage Operation 16-Mb/64-Mb Flash Memories", Yoshikazu Miyawaki et al., IEEE Journal of Solid-State Circuits, vol. 27, No. 4, Apr. 1992, pp. 583-587.
"An Experimental 4-Mb Flash EEPROM with Sector Erase", Mike McConnell et al., IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991, pp. 484-489.
"An In-System Reprogrammable 32KX8 CMOS Flash Memory", Virgil Niles Kynett et al., IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, pp. 1157-1163.
"A 5V Only 16Mbit Flash EEPROM Cell Using Highly Reliable Write/Erase Technologies", N. Kodama, et al., 1991 Symposium on VLSI Technology, pp. 75-76.
"A 4-Mb NAND EEPROM with Tight Programmed Vt Distribution", Masaki Momodomi et al., IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991, pp. 492-495.
"A 3.42 .mu.m2Flash Memory Cell Technology Conformable to a Sector Erase", Hitoshi Kume et al., 1991 Symposium on VLSI Technology, pp. 77-78.
Nikkei Electronics, Feb. 17, 1992 (No. 547), pp. 180-181.
Jacob Millman, Ph.D. et al, Microelectronics Second Edition, McGraw Hill Book Company, 1987, pp. 191-193.
"A High-Density NAND EEPROM with Block-Page Programming for Microcomputer Applications", IEEE Journal of Solid-State Circuits, Yoshihisa Iwata, et al., vol. 25, No. 2, Apr. 1990, pp. 417-424.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Electrically programmable and erasable nonvolatile semiconductor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electrically programmable and erasable nonvolatile semiconductor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electrically programmable and erasable nonvolatile semiconductor will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1109863

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.