Electrically programmable and erasable MOS floating gate memory

Details Electrically programmable and erasable MOS floating gate memory Electrically programmable and erasable MOS floating gate memory

1978-12-15

1980-05-13

Fears, Terrell W.

Static information storage and retrieval

Floating gate

Particular biasing

307238, 357 41, G11C 1140

Patent

active

042031583

ABSTRACT:
An electrically programmable and electrically erasable MOS memory device suitable for high density integrated circuit memories is disclosed. Carriers are tunneled between a floating conductive gate and a doped region in the substrate to program and erase the device. A minimum area of thin oxide (70 A-200 A) is used to separate this doped region from the floating gate. In one embodiment, a second layer of polysilicon is used to protect the thin oxide region during certain processing steps.

REFERENCES:
patent: 3500142 (1970-03-01), Kahng
patent: 4051464 (1977-09-01), Huang

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