Electrically isolated interconnects and conductive layers in sem

Details Electrically isolated interconnects and conductive layers in sem Electrically isolated interconnects and conductive layers in sem

1996-10-15

2000-01-04

Nguyen, Tuan H.

Semiconductor device manufacturing: process

Electron emitter manufacture

445 24, H01L 2100

Patent

active

060109173

ABSTRACT:
A method for fabricating microelectronic deices in which an interconnect layer is electrically isolated from large protuberances that project from a lower conductive layer to a desired endpoint of a chemical-mechanical planarization process. The lower conductive layer is covered with an insulating material to form an insulator layer that generally follows the contour of the lower conductive layer and any large protuberances. A highly conductive interconnect material is then deposited over the insulator layer to form an interconnect layer that generally follows the contour of the insulator layer. The interconnect layer may be deposited directly on the insulator layer, or it may be deposited on an intermediate layer between the interconnect layer and the insulator layer. After the upper conductive layer is deposited, the insulator layer and the upper conductive layer are planarized with a chemical-mechanical planarization process to a desired endpoint.

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