Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-12-18
2003-01-21
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185110, C365S185180
Reexamination Certificate
active
06510081
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an array of FLASH electrically eraseable programmable read-only memory (“FLASH EEPROM”) cells having reduced-page-size erasing and programming. More particularly, the present invention relates to the use of this reduced-page-size FLASH EEPROM in place of state of the art EEPROM in embedded microprocessors for smart card applications.
2. Description of the Related Art
Traditional microprocessor smart card integrated circuits (“ICs”) have used masked ROM and EEPROM for code and data storage respectively. The use of masked ROM for code storage has significant cost and time-to-market disadvantages associated with software changes, especially since smart cards can be extremely software intensive. Specifically, one such disadvantage is the long development time and inherent inflexibility of masked ROM that results in a large undertaking to turn a design and its software into new ICs.
Because traditional EEPROM technology can occupy six times the die area to implement the same memory size as masked ROM, the cost associated with such an increase in die size has prohibited replacing masked ROM with these EEPROM technologies. Additionally, with the ever-increasing die sizes the large size of the EEPROM cells has increased the cost of the silicon.
While FLASH EEPROM technology is considered a viable replacement for EEPROM technology in many applications, its function is not identical to that of EEPROM technology. Unlike an EEPROM which can erase or program byte by byte, a FLASH EEPROM erases or programs large multiple byte size blocks. Specifically, in a FLASH EEPROM a write (i.e. program) of a portion of data that is smaller than the block size starts with a read out of a block of cells into a register. The desired program change is made to the individual cells in the register. Then the block in the FLASH EEPROM array is erased and the reprogrammed register contents are written back into the block.
Several problems occur with this erase and program process in the FLASH EEPROM. First, to erase or program a block of memory in the FLASH EEPROM a register the size of the block is needed. The larger the erasable block the larger the register and the more space on the chip it takes. Secondly, the larger the block size the more data that the microprocessor must handle. This means a larger and more complex microprocessor or much more processing time. Smaller pieces of data are easier for the microprocessor to handle. Thirdly, the FLASH EEPROM endurance is reduced. In many applications, including smart cards, the number of bytes of new data to be written at any one time is small. Since the erase block is relatively large, many bytes in the same block do not need to change data but are nevertheless erased because all bytes contained in the same erase block must be erased simultaneously. Such bytes are first read then erased and re-written with the same data as was held previously. Thus, many bytes experience unnecessary erase and programming cycles that would not otherwise be required, if the erase block was small. The number of times that a single bit can be erased and programmed and still maintain its ability to store data without errors is finite and is referred to as endurance. The unnecessary erase program cycles subtract from the total number of endurance cycles, thus reducing the number of cycles available for useful data changes. It is thus an objective of this invention to have a FLASH EEPROM memory for the microcontroller in a smart card that has reduced size blocks (i.e. page) for erasing or programming.
SUMMARY OF THE INVENTION
The present invention relates the use of FLASH EEPROM technology for both code and data storage on embedded microprocessors for smart card applications. By using FLASH EEPROM technology to replace most of the traditional mask ROM for code storage, the present invention combines the low cost advantages of mask ROM and the re-programmability of traditional EEPROM technology. This enables the user to change and adapt the program code without going through a costly and time-consuming ROM mask change procedure. At the same time, by using the same FLASH EEPROM technology for data storage in place of state of the art EEPROM technology the present invention provides a significant savings in die area and other cost and performance benefits to the user.
More particularly, the present invention relates to reducing the size of the blocks or pages that are contained in a FLASH EEPROM array that must be erased in a write or erase operation. This reduces the size of register needed, makes it easier for the processor to handle smaller blocks of information, reduces the size and complexity of the microprocessor, and increases the endurance of the FLASH EEPROM and allows it to be used in place of the state of the art EEPROM.
Additionally, the replacement of mask ROM by flash EEPROM allows full testing of the code storage area as well as allowing customers to use that space for testing in their manufacturing procedures. The code used for testing can then be cleared and reprogrammed with the final code storage before final shipment.
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Barnett Philip C.
Blyth Trevor
Sowards David
Advanced Technology & Materials Inc.
Chappuis Margaret
Hoang Huan
Zitzmann Oliver A.
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