Static information storage and retrieval – Floating gate – Particular biasing
Patent
1996-11-27
1998-06-30
Nelms, David C.
Static information storage and retrieval
Floating gate
Particular biasing
36518503, 36518524, 365210, G11C 1134
Patent
active
057743959
ABSTRACT:
A reference cell in a nonvolatile memory is electrically erasable and the electrically erasable character of the memory is exploited to expand the voltage range over which a differential amplifier is useful for sensing the state of a bit. Selected elements of a reference cell are electrically erased and reprogrammed for accurately tuning the sensing of multiple data states in a memory cell. For example, 64 or more data states may be tuned so that a single megabyte of memory is allocated to store six megabytes of information.
REFERENCES:
M. Bauer, et al. "A Multilevel-Cell 32Mb Flash Memory", 1995 IEE International Solid State Circuits Conference, Feb. 16, 1995, pp. 132-133.
K. Yoshikawa, "Impact of Cell Threshold Voltage Distribution in the Array of Flash Memories on Scaled and Multilevel Flash Cell Design", 1996 Symposium on VLSI Technology Papers, IEEE, 1996, pp. 240-241.
Garg Shyam
Richart Robert B.
Advanced Micro Devices , Inc.
Koestner Ken J.
Nelms David C.
Niranjan F.
LandOfFree
Electrically erasable reference cell for accurately determining does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Electrically erasable reference cell for accurately determining , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electrically erasable reference cell for accurately determining will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1867126