Electrically erasable PROM cell

Details Electrically erasable PROM cell Electrically erasable PROM cell

1982-07-30

1986-08-26

James, Andrew J.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 54, 365185, H01L 2978, G11C 1150

Patent

active

046085858

ABSTRACT:
In an EEPROM memory cell of the kind which relies on tunneling action through a thin oxide layer to store charge on a floating gate, the floating gate and the channel regions of the memory cell are provided with additional doping of the same kind as in the substrate in order to raise the virgin state threshold voltage of the memory cell to a high positive value, such as 4 volts. Additionally, the overlap area between the control gate and the floating gate is reduced to the extent that the capacitance between the floating gate and the control gate is substantially equal to the capacitance between the floating gate and the substrate during programming, but the effective capacitance between the floating gate and the substrate is greatly reduced during erase mode. As a result, little or no tunneling occurs during programming and the threshold voltage level is the same as the virgin threshold value of the memory cell. However, during erase, very efficient tunneling occurs from the floating gate to the substrate and the threshold voltage level decreases to a negative value. The difference between positive and negative values of the threshold voltage is comparable to that of conventional memory cells.

REFERENCES:
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patent: 3781977 (1974-01-01), Hulmes
patent: 4087795 (1978-05-01), Roessler
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patent: 4203158 (1980-05-01), Frohman-Bentchkowsky et al.
patent: 4209849 (1980-06-01), Schrenk
patent: 4254427 (1981-03-01), Lohstroh
patent: 4467452 (1984-08-01), Saito et al.
IBM Technical Disclosure Bulletin, vol. 22, #1, Jun. 79, "Stacked Gate Device With Reduced O State Threshold Voltage", by Jambothan and Chang, p. 160.

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