Electrically erasable programmable read-only memory with write/v

Details Electrically erasable programmable read-only memory with write/v Electrically erasable programmable read-only memory with write/v

1994-04-05

1995-01-03

LaRoche, Eugene R.

Static information storage and retrieval

Floating gate

Particular biasing

36518901, 36518909, G11C 700

Patent

active

053792564

ABSTRACT:
A plurality of electrically erasable programmable read-only memories or EEPROMs are associated with a controller LSI. Each EEPROM includes an array of floating-gate tunneling memory cell transistors arranged in rows and columns. When a sub-array of memory cell transistors providing a one-page data is selected for programming, the controller LSI performs a write/verify operation as follows the electrically written state after the programming of the selected memory cell transistors is verified by checking their threshold values for variations, and when any potentially insufficient cell transistor remains among them, the rewrite operation using a predetermined write voltage for a predetermined period of time is repeated so that the resultant write state may come closer to a satisfiable reference state. Each rewrite/verify operation is performed by applying the write voltage to the insufficient cell transistor for a predetermined period of time.

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patent: 5053990 (1991-10-01), Kreifels et al.
patent: 5124945 (1992-06-01), Schreck
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Franzis-Verlag, Munich, 1984, pp. 374-275, D. Nuhrmann, "Das Grosse Werkbuch Elekrtonik".

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