Electrically erasable programmable read-only memory with NAND me

Details Electrically erasable programmable read-only memory with NAND me Electrically erasable programmable read-only memory with NAND me

1990-12-26

1992-02-11

Fears, Terrell W.

Static information storage and retrieval

Floating gate

Particular biasing

36518901, 36523001, G11C 1140

Patent

active

050880608

ABSTRACT:
An electrically erasable programmable read-only memory with a NAND cell structure has parallel bit lines, and memory cells defining NAND cell blocks, each of which has a series-circuit of memory cell transistors. Each transistor has a floating gate and a control gate. Parallel word lines are connected to the control gates of the cell transistors. The first, second and third intermediate voltages are used in the data write mode: the first voltage is lower than the "H" level voltage and higher than the "L" level voltage; the second and third voltages are higher than the first voltage and lower than the "H" level voltage. Data is written into a selected memory cell transistor of a NAND cell block, by applying the "H" level voltage to a word line connected to the selected transistor, applying the second voltage to the remaining unselected word lines, applying a corresponding bit line associated with the selected transistor with one of the first and third voltages which is selected in accordance with a logic level of the data, and applying unselected bit lines with the third voltage, whereby carriers are moved by tunneling from or to the floating gate of the selected memory cell transistor.

REFERENCES:
patent: 4233526 (1980-11-01), Kurugi et al.
patent: 4677590 (1987-06-01), Arakawa
patent: 4694317 (1987-09-01), Terula
patent: 4996669 (1991-02-01), Endoh et al.

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