Electrically erasable programmable read-only memory with NAND ce

Details Electrically erasable programmable read-only memory with NAND ce Electrically erasable programmable read-only memory with NAND ce

1988-12-27

1990-07-03

Hecker, Stuart N.

Static information storage and retrieval

Floating gate

Particular biasing

365184, 3652385, 365218, 357 235, G11C 1140, G11C 1700

Patent

active

049396900

ABSTRACT:
An erasable programmable read-only memory with NAND cell structure is disclosed which includes NAND cell blocks each of which has a selection transistor connected to a corresponding bit line and a series array of memory cell transistors. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data erase mode all the memory cells are simultaneously erased by applying a "H" level potential to the control gates of the memory cells and a "L" level potential to the bit lines. Prior to such a simultaneous erase, charges are removed from charge accumulation layers of the memory cells so that the threshold values of the memory cells are initialized. The threshold initialization is performed on the series-arrayed memory cell transistors in the NAND cell block in sequence.

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IBM Technical DIsclosure Bulletin, vol. 24, No. 7B, Dec. 81, pp. 3811-3812, "Electrically Alterable Non-Volatile Logic Circuits" by Kotecha.

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