Static information storage and retrieval – Floating gate – Particular connection
Patent
1995-04-28
1998-07-07
Popek, Joseph A.
Static information storage and retrieval
Floating gate
Particular connection
365104, 257316, G11C 1700
Patent
active
RE0358380
ABSTRACT:
An erasable programmable read-only memory with NAND cell structure is disclosed which has memory cells provided on a N type substrate. The memory cells are divided into NAND cell blocks each of which has a series array of memory cell transistors. Each of the transistors has a floating gate, a control gate connected to a word line and N type diffusion layers serving as its source and drain. These semiconductor layers are formed in a P type well layer formed in a surface area of a substrate. The well layer serves as a surface breakdown prevention layer. During a data erase mode data stored in all the memory cells are erased simultaneously. During the data write mode subsequent to the erase mode, when a certain NAND cell block is selected, memory cells in the NAND cell block are subjected to data writing in sequence. When data is written into a certain memory cell in the selected NAND cell block, a control gate of the certain memory cell is supplied with a voltage which is so high as to form a strong electric field to allow the tunneling of electrons between the floating gate of the memory cell and the well layer. Consequently, only the selected cell can be written into.
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Itoh Yasuo
Kirisawa Ryouhei
Masuoka Fujio
Momodomi Masaki
Ohuchi Kazunori
Ho Hoai V.
Kabushiki Kaisha Toshiba
Popek Joseph A.
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