Electrically erasable programmable read-only memory with electri

Details Electrically erasable programmable read-only memory with electri Electrically erasable programmable read-only memory with electri

1994-02-24

1995-03-28

LaRoche, Eugene R.

Static information storage and retrieval

Floating gate

Particular biasing

365218, 257316, G11C 1134

Patent

active

054023734

ABSTRACT:
A NAND cell type EEPROM has bit lines, each of which is associated with a NAND cell unit including a series array of four memory cell transistors. Each transistor is a MOSFET with a control gate and a floating gate for data storage. The memory cell transistors are connected at their control gates to word lines, respectively. One end of the NAND cell unit is connected through a first select transistor to a corresponding bit line; the other end thereof is connected via a second select transistor to a source voltage. The memory cell transistors and the select transistors are arranged in a well region formed in a substrate. In an erase mode, the bit line voltage, the substrate voltage and the well voltage are held at a high voltage, whereas the word lines are at zero volts. The gate potential of the select transistors is held at the high voltage, whereby the internal electric field of these select transistors is weakened to improve the dielectric breakdown characteristic thereof.

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1986 Symposium of VLSI Technology; May 28-30, 1986/San Diego; R. Stewart, et al.; "A High Density EPROM Cell And Array"; pp. 89-90.
RCA David Sarnoff Research Ctr., Rte. 1, Princeton, N.J., VII-9, R. Stewart, et al., "A High Density EPROM Cell And Array", pp. 89-90.
IBM Technical Disclosure Bulletin, vol. 27, No. 6, Nov. 1984, E. Adler, "Densely Arrayed EEPROM Having Low-Voltage Tunnel Write", pp. 3302-3307.

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