Electrically erasable programmable read-only memory and...

Details Electrically erasable programmable read-only memory and... Electrically erasable programmable read-only memory and...

2002-05-24

2003-11-25

Mai, Son (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185140, C365S185310

Reexamination Certificate

active

06654291

ABSTRACT:

CROSS-REFERENCES TO RELATED APPLICATIONS
This application claims priority from R.O.C. Patent Application No. 090114542, filed Jun. 15, 2001, the entire disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates generally to semiconductor devices and, more particularly to an electrically erasable programmable read-only memory.
FIG. 1A
is a top-view diagram showing a conventional EEPROM (electrically erasable programmable read-only memory). Memory
1
comprises memory cells
11
arranged in a matrix. Each of the memory cells
11
has a floating gate
14
, a drain region
16
and a plug
18
connected to the drain region
16
. A doped region
15
is formed to be a common source for the memory cells
11
in two adjacent columns. The memory cells in one column have a common select gate
12
and a common control gate
13
. A conducting line
17
electrically connects the drain regions
16
of the memory cells
11
in one line through the plugs
18
.
FIG. 1B
is a cross-section showing one of the memory cells
11
. The memory cell
11
has a substrate
10
. The control gate
13
, floating gate
14
and select gate
12
are stacked on the substrate
10
. A thin oxide
19
is formed between the gates
12
,
13
,
14
and the substrate
10
. The substrate
10
has doped regions for the source
15
and drain
16
. The plug
18
is connected to the drain
16
, as previously described. Bias voltages SG, CG, CS and D are applied to the select gate
12
, control gate
13
, common source
15
and drain
16
respectively. TABLE 1 shows values of the bias voltages applied during reading, programming and erasing.
TABLE 1
Program
Erase
Read
SG
1.7
0
0
4.4
CG
8.5
0
−9
1.6
CS
6
12
6
0
D
0
0/Floating
1.5
In TABLE 1, it is noted that a high voltage difference is generated between the source
15
and the floating gate
14
by applying a 12V bias voltage to the source
15
when erasing the memory cell
11
, whereby the charges stored in the floating gate
14
are forced to flow into the substrate
10
. Alternatively, the high voltage difference between the source
15
and the floating gate
14
can be derived by applying a −9V bias voltage to the control gate
13
which will be coupled to the floating gate
14
and a 6V bias voltage to the source
15
. Therefore, the erasing of the memory cell
11
is determined by the bias voltage CG and CS respectively applied to the control gate
13
and common source
15
while the bias voltage SG and D are 0 or floating.
However, all the memory cells
11
in one column are erased simultaneously since their control gates are electrically connected and their sources are electrically connected, i.e., they receive the same bias voltage CG for the control gates and the same bias voltage CS for the common sources. It is impossible to erase only one memory cell
11
in the conventional EEPROM. The invention provides a solution for this problem.
BRIEF SUMMARY OF THE INVENTION
Embodiments of the present invention are directed to an improved EEPROM in which the memory cells can be selectively erased. If the control gates of the memory cells are electrically connected, their sources are electrically isolated from each other, so that the memory cells may receive a common bias voltage for the control gates but different bias voltages for the sources. It is possible to erase only one memory cell by providing the to-be-erased memory cell with a bias voltage for the source different from the bias voltage provided to the sources of the other memory cells. Alternatively, if the same bias voltage is provided to the sources of the memory cells, their control gates are electrically isolated from each other, so that the memory cells may receive different bias voltages for the control gates. It is possible to erase only one memory cell by providing the to-be-erased memory cell with a bias voltage for the control gate different from the bias voltage provided to the control gates of the other memory cells.
In accordance with an aspect of the present invention, an electrically erasable programmable read-only memory comprises a first memory cell having a first control gate and a first source, and a second memory cell having second control gate and a second source. If the first and second control gates are configured to receive a control gate voltage, the first source is configured to receive a first source voltage, and the second source is configured to receive a second source voltage different from the first source voltage so as to erase one of the first and second memory cells and to preserve another of the first and second memory cells. If the first and second sources are configured to receive a source voltage, the first control gate is configured to receive a first control gate voltage, and the second control gate is configured to receive a second control gate voltage different from the first control gate voltage so as to erase one of the first and second memory cells and to preserve another of the first and second memory cells.
In some embodiments, the first memory cell comprises a first floating gate, a first select gate, and a first drain; and the second memory cell comprises a second floating gate, a second select gate, and a second drain. The first drain and the second drain are electrically coupled together. The first select gate and the second select gate are electrically coupled together. The first source voltage is sufficiently higher than the control gate voltage to erase the first memory cell and the second source voltage is not sufficiently higher than the control gate voltage to erase the second memory cell.
In some embodiments, the first source voltage is higher than the control gate voltage by at least about 12V. The second source voltage is higher than the control gate voltage by no more than about 9V, or by no more than about 6V.
In specific embodiments, the first and second control gates have a control gate voltage of about −9V, the first source has a first source voltage of at least about 6V, and the second source has a second source voltage of no greater than about 0V. The first and second control gates each have a control gate voltage of about 0V, the first source has a first source voltage of at least about 12V, and the second source has a second source voltage of no greater than about 0V. The first and second sources have a source voltage of about 6V, the first control gate has a first control gate voltage of no greater than about −9V, and the second control gate has a second control gate voltage of at least about 0V. The first and second sources have a source voltage of about 12V, the first control gate has a first control gate voltage of no greater than about 0V, and the second control gate has a second control gate voltage of at least about 6V.
Another aspect of the present invention is directed to an erasing method for an electrically erasable programmable read-only memory having a first memory cell and a second memory cell, wherein the first memory cell has a first control gate and a first source and the second memory cell has second control gate and a second source. The method comprises either (1) providing a control gate voltage to the first and second control gates, providing a first source voltage to the first source, and providing a second source voltage to the second source which is different from the first source voltage so as to erase one of the first and second memory cells and to preserve another of the first and second memory cells; or (2) providing a source voltage to the first and second sources, providing a first control gate voltage to the first control gate, and providing a second control gate voltage to the second control gate which is different from the first control gate voltage so as to erase one of the first and second memory cells and to preserve another of the first and second memory cells.


REFERENCES:
patent: 5753953 (1998-05-01), Fukumoto
patent: 5801993 (1998-09-01), Choi

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