Static information storage and retrieval – Floating gate – Particular biasing
Patent
1982-02-18
1984-10-16
Popek, Joseph A.
Static information storage and retrieval
Floating gate
Particular biasing
357 23, G11C 1140
Patent
active
044778830
ABSTRACT:
In an electrically erasable and programmable read only memory of this invention, each memory cell has an L-shaped floating gate insulated from a substrate. The floating gate and a first control gate, the floating gate and a second control gate, and the floating gate and a source electrode connected to a source are capacitively coupled at predetermined capacitances, respectively. A projecting portion which is formed in the source electrode underlies a coupling region of first and second gate portions of the floating gate. When a voltage of +20 V is applied to the source electrode and a voltage of 0 V is applied to the first and second gates, electrons stored in the floating gate of at least one desired memory cell may be discharged.
REFERENCES:
patent: 3728695 (1973-04-01), Frohman-Bentchkowsky
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patent: 4099196 (1978-07-01), Simko
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Electronics/Feb. 28, 1980, pp. 113-117, "16-K EE-Prom Relies on Tunneling for Byte-Erasable Program Storage", Johnson et al.
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IEEE Transactions on Electron Devices, vol. ED-24, No. 5, (May 1977), J. Kupec et al., "Triple Level Poly Silicon E2prom With Single Transistor Per Bit," pp. 602-606.
Popek Joseph A.
Tokyo Shibaura Denki Kabushiki Kaisha
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