Electrically erasable programmable non-volatile semiconductor me

Details Electrically erasable programmable non-volatile semiconductor me Electrically erasable programmable non-volatile semiconductor me

1994-10-06

1996-06-04

Fears, Terrell W.

Static information storage and retrieval

Floating gate

Particular connection

36518506, 257344, 257316, G11C 1300

Patent

active

055239692

ABSTRACT:
A flash memory includes a plurality of blocks each having a plurality of memory cells located at intersections between a plurality of row lines and at least one sub column line, and at least one main column line connected to said at least one sub column line of each of said blocks through a selection transistor. Both of said memory cells and said selection transistor have a floating gate electrode and a control gate electrode. The selection transistor has a drain region of the lightly doped drain structure in which a low impurity concentration diffused region is located at a channel side thereof.

REFERENCES:
patent: 5218569 (1993-06-01), Banks
H. Onoda, et al., "A Novel Cell Structure Suitable for a 3 Volt Operation, Sector Erase Flash Memory", IEEE, IEDM 92, pp. 599-602, 1992.
M. Momodomi, et al., "New Device Technologies for 5V-Only 4Mb EEPROM With NAND Structure Cell", IEEE, IEDM 88, pp. 412-415, 1988.

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