Static information storage and retrieval – Read only systems – Semiconductive
Patent
1986-02-07
1988-05-17
Popek, Joseph A.
Static information storage and retrieval
Read only systems
Semiconductive
364716, 307465, G11C 1700, H03K 19177
Patent
active
047455799
DESCRIPTION:
BRIEF SUMMARY
FIELD OF INVENTION
This invention relates to systems which can be reconfigured and, in particular, to electrically erasable systems that can be repeatedly reconfigured.
BACKGROUND OF INVENTION
Associative memories and Programmable Logic Arrays (PLAs) are typically programmed by the manufacturer or are programmed in the field by electrically opening (blowing) fusible links to establish the memory stored or the logic functions desired. Known commercially available programmable Associative memories and programmable PLA's can be configured only once. The book entitled "Introduction to VSLI Systems" by Carver Mead (one of the present inventors) et al, pages 80-82, illustrates a programmable logic array having two arrays of memory cells with each memory cell being a single conventional field effect transistor. The presence or absence of a transistor in any location of either array is indicative of a "1" and "0", respectively, stored at that location. The presence or effective absence of a transistor at a particular memory location is either set by the manufacturer or is established by blowing fusible links either electrically or with a laser.
The publication entitled "High Performance MOS EPROMs Using a Stacked Gate Cell," International Solid State Circuits Conference Digest of Technical Papers, page 186, February 1977, describes nonvolatile devices which are erased by exposing them to ultraviolet light. The need to have a source of ultraviolet light and to package the devices such that they could easily be exposed to ultraviolet light, as well as poor reproducibility and fast wear out during program/erase cycling, limits the use of this device.
The publication entitled "A 16 Kb Electrically Erasable Nonvolatile Memory," International Solid State Circuits Conference Digest of Technical Papers, pages 152 and 153, describes a nonvolatile device, denoted as FLOTOX (floating gate tunnel oxide), which consists of two field effect transistors which are serially connected together with the source of the first connected to the drain of the second. The first transistor, which is denoted as a select transistor, is a conventional field effect transistor. The second transistor, which is denoted as a memory transistor, is a field effect transistor which has a floating gate structure in addition to a gate terminal to which control voltages are directly applied. The floating gate has a portion which is separated from a major surface of the semiconductor substrate by a thin silicon dioxide layer denoted as tunnel oxide. The FLOTOX cell, which is implemented using n-channel transistors, is both programmed and erased by applying appropriate potentials to the gate terminals of both transistors, to the drain terminal of the select transistor, and to the source terminal of the memory transistor. The FLOTOX cells are illustrated in a memory array having two rows of memory cells and two columns. The cell and the basic form of the array were used to form a 16K EEPROM.
It is desirable to incorporate EEPROM technology in associative memories and PLAs in order to allow same to be repeatedly reconfigured by an end user or by a run-time self adjusting reconfigurable control system.
SUMMARY OF INVENTION
The present invention relates to circuitry which can be used as part of an associative memory or a programmable logic array (PLA) which can both be repeatedly reconfigured by an end user or by a run-time self adjusting reconfigurable control system. In one embodiment the circuitry comprises a first array of rows and columns of devices with each device comprising electrically erasable upper and lower memory cells that each have a control terminal and an input/output terminal. First and second select lines of a separate pair of a plurality of select lines are coupled to the control terminals of the upper and lower memory cells, respectively, of the devices of a separate row of devices. A separate one of a plurality of bit lines is coupled to the upper and lower memory cells of the devices of a separate column of devices. Select line mean
REFERENCES:
patent: 4064494 (1977-12-01), Dickson et al.
patent: 4068305 (1978-01-01), Cutler
patent: 4313106 (1982-01-01), Hsu
patent: 4490812 (1984-12-01), Guterman
Mead Carver
Shen Cecilia
Ostroff Irwin
Popek Joseph A.
Silicon Communications Corporation
LandOfFree
Electrically erasable programmable logic array (EEPLA) does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Electrically erasable programmable logic array (EEPLA), we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electrically erasable programmable logic array (EEPLA) will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1886108