Electrically erasable programmable electronic circuits using pro

Details Electrically erasable programmable electronic circuits using pro Electrically erasable programmable electronic circuits using pro

1984-07-05

1986-06-24

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307450, 307451, 307968, 307469, 365185, G11C 1140

Patent

active

045969388

ABSTRACT:
The series connection between operating voltage terminals of the channels of field effect transistors with electrically alterable threshold voltage, programmed one for conduction and the other for non-conduction in response to programming voltage on their gate-to-gate connection, forms a programmable latch. A pair of such latches, or such a latch and a complementary-pair logic inverter, form a programmable complemented latch. The programmable complemented latch can be used to selectively enable a complementary-pair transmission gate, or to selectively enable a complementary-pair logic inverter, or to alternatively enable a transmission gate and a logic inverter. This last operation can be carried out, for example, in a modified Annis exclusive-OR gate configuration, for selectively inverting or not inverting a logic input.

REFERENCES:
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patent: 4228527 (1980-10-01), Gerber et al.
patent: 4495427 (1985-01-01), Cartwright, Jr.
patent: 4509070 (1985-04-01), Furumura
patent: 4516313 (1985-05-01), Turi et al.
Krick, "Complementary MNOS Electronically Alterable Read-Only Memory", IBM TDB, vol. 13, No. 1, Jun. 1970, pp. 263-264.
Kotecha, "Electrically Alterable Non-Volatile Logic Circuits", IBM TDB, vol. 24, No. 7B, Dec. 1981, pp. 3811-3812.
FET Enchancement/Depletion Logic Circuit, by R. W. Knepper, IBM Technical Disclosure Bulletin, vol. 20, No. 4, Sep. 1977.
"CMOS Technologie-Basis for Die Zukunft", G Auderer der Electtoniker, No. 11, 1981, pp. 53-56.
Patent Abstracts of Japan, vol. 3, No. 99, Jun. 1979, p. 143, E 132, re JPA 54-78679, Fujitsu K. K. Kokai.

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