Electrically erasable nonvolatile memory having discharging circ

Static information storage and retrieval – Floating gate – Particular biasing

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Details

365185, 36518909, 365226, 36523006, G11C 1602

Patent

active

055026796

ABSTRACT:
When power is turned off during erasure or writing of an EEPROM, electric charge remains on the bit and word selecting lines and on the control line due to the high voltage applied to write or erase data. This charge is discharged through the memory cells when the power is turned on. Erroneous erasure, erroneous writing, and erroneous reading are prevented by including a reset circuit for producing a reset signal when the power is turned on. A bias circuit is connected to the reset circuit for producing a predetermined voltage during the period of the reset signal. A driver circuit receptive of the reset signal selects and drives all word lines with the predetermined voltage during the period of the reset signal, and discharging circuits are provided for electrically discharging all control lines and all bit lines during the period of the reset signal. When the device is turned on, the reset signal is generated, thereby discharging the bit lines and control lines.

REFERENCES:
patent: 4905197 (1990-02-01), Urai
patent: 5138575 (1992-08-01), Ema et al.

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