Electrically erasable nonvolatile memory

Details Electrically erasable nonvolatile memory Electrically erasable nonvolatile memory

1998-08-20

1999-11-02

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518518, 36518527, 365218, G11C 1604

Patent

active

059782765

ABSTRACT:
A nonvolatile memory cell which is highly scalable includes a cell formed in a triple wall. The control gate is negatively biased. By biasing the P-well and drain (or source) positively within a particular voltage range when erasing, GIDL current and degradation from a hole trapping can be diminished and hence scalable technology may be achieved.

REFERENCES:
patent: 5235544 (1993-08-01), Caywood
patent: 5341342 (1994-08-01), Brahmbhatt
patent: 5349220 (1994-09-01), Hong
patent: 5416738 (1995-05-01), Shrivastava
patent: 5457652 (1995-10-01), Brahmbhatt
patent: 5657271 (1997-08-01), Mori
patent: 5677868 (1997-10-01), Takahashi et al.
patent: 5742541 (1998-04-01), Tanigami et al.

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