Electrically erasable non-volatile semiconductor device

Details Electrically erasable non-volatile semiconductor device Electrically erasable non-volatile semiconductor device

1989-01-27

1990-12-18

Popek, Joseph A.

Static information storage and retrieval

Floating gate

Particular biasing

365218, 357 235, G11C 1134, H01L 2348

Patent

active

049791460

ABSTRACT:
In an electrically erasable non-volatile semiconductor memory device, a plurality of non-volatile semiconductor memory cells are arranged in a matrix form and are connected to corresponding ones of row and column lines. In a data writing mode, a first voltage Vp at is applied to the column lines so that the drains of the memory cells are maintained at a drain potential, and a second voltage is applied to the row lines so that a sum level of the drain potential and the threshold voltage of the memory cell is not smaller than the floating gate potential of the memory cell.

REFERENCES:
patent: 4466081 (1984-08-01), Masuoka
patent: 4597062 (1986-06-01), Asano et al.

Affiliated with

Also associated with

Rating

Electrically erasable non-volatile semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electrically erasable non-volatile semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electrically erasable non-volatile semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1430147