Electrically erasable non-volatile memory cell with integrated S

Details Electrically erasable non-volatile memory cell with integrated S Electrically erasable non-volatile memory cell with integrated S

1999-05-26

2000-09-12

Mai, Son

Static information storage and retrieval

Floating gate

Particular connection

3651851, 36518908, 326 38, 326 39, G11C 1604

Patent

active

061186937

ABSTRACT:
In a programmable integrated circuit, by providing a static random access memory (SRAM) cell in each electrically erasable (E.sup.2) non-volatile memory cell, testing time of circuits configured by the E.sup.2 non-volatile memory cells can be reduced substantially. In one embodiment, the SRAM cell can be included by providing a small number of transistors to recirculate the output value of an inverting buffer. During testing, a logic value is written into the SRAM cell in place of the logic value in the non-volatile storage of the E.sup.2 non-volatile memory cell. In one embodiment, the E.sup.2 non-volatile memory cell can be used in conjunction with a 1-bit shift-register. Multiple 1-bit shift registers can be used as a scan chain to scan into the SRAM cells of multiple E.sup.2 non-volatile memory cells.

REFERENCES:
patent: 5272368 (1993-12-01), Turner et al.
patent: 5548228 (1996-08-01), Madurawe
patent: 5815726 (1998-09-01), Cliff
patent: 5818254 (1998-10-01), Agrawal et al.

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