Electrically erasable fused programmable logic array

Details Electrically erasable fused programmable logic array Electrically erasable fused programmable logic array

1985-03-22

1988-11-22

Harkcom, Gary V.

Boots, shoes, and leggings

307465, G06F 738

Patent

active

047870478

ABSTRACT:
A programmable logic gate array employing a plurality of reprogrammable fuses having a logical NAND characteristic for logically connecting selected inputs to selected logic gates. The fuses are selectively programmed for providing appropriate signals to allow three modes of operation of the logic gate array; programming, erasure and normal logic operation.

REFERENCES:
patent: 4399523 (1983-08-01), Gerber et al.
patent: 4422072 (1983-12-01), Cavlan
patent: 4490812 (1984-12-01), Guterman
patent: 4495427 (1985-01-01), Cartwright, Jr.
patent: 4503520 (1985-03-01), Kyomasu et al.
patent: 4508977 (1985-04-01), Page et al.
patent: 4546273 (1985-10-01), Osman
patent: 4546454 (1985-10-01), Gupta et al.
patent: 4558344 (1985-12-01), Perlegos
patent: 4580247 (1986-04-01), Adam
patent: 4596938 (1986-06-01), Cartwright, Jr.
Roth, Jr., "Fundamentals of Logic Design", West Publishing Company, Second edition, 1979, p. 511.
Hsieh et al., "Electrically Aterable Programmable Logic Array (EAPLA)", International Electron Devices Meeting Technical Digest, Publ.:IEEE, 1980, pp. 598-601.

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