Electrically-erasable, electrically-programmable read-only memor

Details Electrically-erasable, electrically-programmable read-only memor Electrically-erasable, electrically-programmable read-only memor

1991-07-15

1993-04-06

Clawson, Jr., Joseph E.

Static information storage and retrieval

Floating gate

Particular biasing

36518909, 365218, 257321, 257322, 257369, G11C 1140

Patent

active

052009190

ABSTRACT:
A field effect transistor memory cell having a selectable threshold voltage is formed in a semiconductor layer (18). An n-channel electrically-erasable, electrically-programmable read-only memory cell (12) is formed and includes a source (14) and a drain (16) separated by a channel (20), a tunneling window (22) adjacent drain (16), a floating gate (24) and a control gate (26) capacitively coupled to channel (20). N-channel memory cell (12) is operable to charge and discharge floating gate (24) by Fowler-Nordheim tunneling upon the application of voltages to control gate (26) and drain (16). A p-channel field effect transistor (30) is formed and includes a source (34) in a drain (36) spaced by a channel (38). Floating gate (24) is insulatively disposed adjacent channel (38) such that the conductance of channel (38) is controlled by floating gate (24). A threshold control circuit (76) is provided for biasing channel (38) of p-channel field effect transistor (30) in relationship to control gate (26). A monitoring circuit (90) controls the application of voltage to control gate (26) in response to conduction between source (34) and drain (36) of p-channel field effect transistor (30).

REFERENCES:
patent: 4595999 (1986-06-01), Betirac
patent: 4686558 (1987-08-01), Adam
patent: 4791317 (1988-12-01), Winnerl et al.
patent: 4797856 (1989-01-01), Lee et al.
patent: 4798974 (1989-01-01), Reczek et al.
patent: 4829203 (1989-05-01), Ashmore
patent: 5043940 (1991-08-01), Harari

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