Electrically-erasable, electrically-programmable read-only memor

Details Electrically-erasable, electrically-programmable read-only memor Electrically-erasable, electrically-programmable read-only memor

1990-03-15

1991-04-16

Hille, Rolf

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 54, 365185, H01L 2968, H01L 2934, G11C 1134

Patent

active

050087215

ABSTRACT:
An electrically-erasable, electrically-programmable ROM or an EEPROM is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small self-aligned tunnel window positioned on the opposite side of the source from the channel and drain, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. In this cell, the bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window area on the outside of the source (spaced from the channel). The tunnel window has a thinner dielectric than the remainder of the floating gate to allow Fowler-Nordheim tunneling.

REFERENCES:
patent: 4180826 (1979-12-01), Shappir
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patent: 4590504 (1986-05-01), Suterman
patent: 4622737 (1986-11-01), Ravaglia
patent: 4668970 (1987-05-01), Yatsuda et al.
patent: 4686558 (1987-08-01), Adam
patent: 4750024 (1988-06-01), Schreck

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