Electrically erasable and programmable semiconductor memory devi

Details Electrically erasable and programmable semiconductor memory devi Electrically erasable and programmable semiconductor memory devi

1992-06-05

1994-08-16

Jackson, Jerome

Spring devices

Vehicle

Lever and nontorsion spring

257321, 257331, H01L 2968

Patent

active

053389530

ABSTRACT:
A p-type silicon substrate 1 is provided with a trench 11. A second gate oxide film 4 is formed on a bottom wall 11a of the trench. The trench has a side wall 11b on which a first gate oxide film 9 is formed. A thickness of the second gate oxide film 4 is smaller than that of the first gate oxide film 9. A floating gate electrode 5 is formed on the second and first gate oxide films 4 and 9. At the vicinities of the opposite ends of the floating gate electrode 5, there are formed an n.sup.+ -drain diffusion region 2 and n.sup.+ -source diffusion region 3. A control gate electrode 7 is formed over the floating gate electrode 5 with an layer insulating film 6 interposed therebetween. In an electrically programmable and erasable semiconductor memory device (EEPROM) of a flash type, a writing efficiency is improved, a reliability is improved with respect to quality control, and dimensions of memory transistors are reduced.

REFERENCES:
patent: 4796228 (1989-01-01), Baglee
patent: 4868619 (1989-09-01), Mukherjee et al.
patent: 4929988 (1990-05-01), Yoshikawa
patent: 4972371 (1990-11-01), Komori et al.
patent: 5045490 (1991-09-01), Esquivel
patent: 5180680 (1993-01-01), Yang
Yoshikawa et al., "A Reliable Profiled Lightly Doped Drain (PLD) Cell for High-Density Submicrometer EPROM's and Flash EEPROM's", IEEE Transactions on Electron Devices, vol. 37, No. 4, Apr. 1990, pp. 999-1005.
"An In-System Reprogrammable 32K X 8 CMOS Flash Memory", by Virgil N. Kynett et al., IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, pp. 1157-1163.

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