Static information storage and retrieval – Addressing – Plural blocks or banks
Patent
1993-01-19
1994-03-22
LaRoche, Eugene R.
Static information storage and retrieval
Addressing
Plural blocks or banks
365185, 365900, 36518901, G11C 700
Patent
active
052971031
ABSTRACT:
An electrically erasable and programmable memory device includes a memory cell array including a plurality of blocks, each including electrically erasable and programmable memory cells. A data input/output unit transfers data between the memory cell array and an external device. An address conversion unit converts an external address signal into a decoded signal applied to the memory cell array so that the correspondence between the external address and the plurality of blocks is changed so as to equally access the plurality of blocks for programming. The number of the plurality of blocks is greater than the number of blocks accessible by the external address signal.
REFERENCES:
patent: 4718038 (1988-01-01), Yoshida
patent: 5210716 (1993-05-01), Takada
Fujitsu Limited
LaRoche Eugene R.
Le Vu A.
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