Electrically erasable and programmable semiconductor memory

Details Electrically erasable and programmable semiconductor memory Electrically erasable and programmable semiconductor memory

2000-12-28

2002-01-08

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185180

Reexamination Certificate

active

06337807

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-375482, filed Dec. 28, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory and, more particularly, to an electrically erasable and programmable ROM (to be referred to as an EEPROM hereinafter) having NAND memory cells.
EEPROMs are conventionally known as one type of semiconductor memories. Of these EEPROMs, a NAND cell type EEPROM in which a plurality of memory cells are connected in series to form a NAND memory cell is attracting attention as a device which can be highly integrated.
One memory cell in this NAND cell type EEPROM has a MOSFET structure in which a floating gate (a charge storage layer) and a control gate are stacked via an insulating film on a semiconductor substrate. A plurality of such memory cells are connected in series to form a NAND cell such that adjacent memory cells share the source and drain. Such NAND cells are arrayed in a matrix manner to form a memory cell array.
Memory cell arrays are integrated in a p-type-well formed on a p-type-substrate. An n-type-well is first formed on the p-type-substrate, and then the p-type-well for integrating memory cell arrays is formed in this n-type-well.
Drains on the one-end side of a plurality of memory cell arrays arranged in the column direction are connected together to a bit line via select transistors. Sources on the other-end side are connected to a common source line (reference voltage line) via select transistors. The control gates of memory cell transistors are connected to word lines. The gates of the select transistors are connected to select lines.
The operation of this NAND EEPROM will be described below by taking a device in which n-channel transistors are used as memory cell transistors as an example.
Data programming is performed as follows. Data is written in turn from a memory cell farthest from the bit line. A high voltage Vpp (about 20 V) is applied to the control gate of a selected memory cell. An intermediate voltage VppM (about 10 V) is applied to the control gates of memory cells and the gate of the select transistor closer to the bit line than the selected memory cell. The bit line is given a predetermined voltage in accordance with the data, e.g., given 0 V when the data is “0” and an intermediate voltage when the data is “1”. The power supply voltage is applied to the select line on the bit line side, and the ground voltage is applied to the select line on the source line side. In this state, the voltage of the bit line is transmitted to the drain of the selected memory cell through the select transistor and unselected memory cells.
When 0 V is applied to the bit line (when write data exists, i.e., when data is “1”), this voltage is transmitted to the drain of the selected memory cell to apply a high electric field between the gate and drain of the selected memory cell. Hence, electrons are injected (tunnel-injected) from the drain (substrate) into the floating gate. Consequently, the threshold voltage of the selected memory cell shifts in the positive direction.
On the other hand, when the intermediate voltage is applied to the bit line (when no data to be written exists, i.e., when data is “1”), no electron injection occurs, so the threshold voltage remains unchanged, i.e., negative.
Data erase is performed as follows.
First, in a selected NAND cell block, the ground voltage is applied to the control gates of all memory cells in the block. In an unselected NAND cell block, the control gates of all memory cells in the block and all select lines, bit lines, and source lines are floating. Subsequently, a high erase voltage (about 20 V) is applied to p- and n-type-wells. Consequently, electrons are emitted into the wells from the floating gates of the memory cells in the selected block, erasing the data in the memory cells in the block.
In this state, the control gates of the memory cells, select lines, bit lines, and source lines in the unselected NAND cell block raise their voltages close to the erase voltage by capacitive coupling. For example, the voltage of the select line rises close to the erase voltage (about 20 V) by the capacitive coupling of the gate capacitance of the select transistor with the other parasitic capacitance in the select line.
Data read is performed as follows.
First, the control gate of a selected memory cell is set at 0 V, and the control gates of other memory cells and the select lines are set at a read voltage (about 3.5 V), thereby turning on unselected memory cell transistors and select transistors. Each data of “1” and “0” is discriminated by sensing whether a current flows or not into the bit line respectively.
As described above, different voltages are supplied to the select lines and the word lines connected to the control gates in the data programming, erase, and read modes.
FIG. 1
shows a circuit configuration for supplying voltages to select lines and word lines of NAND cells (of n-th blocks).
Referring to
FIG. 1
, transistors MN
1
-
0
to MN
1
-
19
are high-breakdown-voltage transistors having a thick gate insulating film. They permit a high voltage to be applied to their nodes. Portions R
1
to Rn enclosed by the broken lines indicate row selecting means (row decoders) of blocks C
1
to Cn. These blocks C
1
to Cn represent memory cell arrays in these blocks. For the sake of simplicity, only one bit line is shown in FIG.
1
. It is appreciated that multiple bit lines exist and are known in the art. The circuit configuration will be explained by using the circuit of the first block.
Memory cells MC
1
to MC
16
are connected in series. One end of a current path of a select transistor SD
1
is connected to the drain of the memory cell MC
1
. One end of a current path of a select transistor SS
1
is connected to the source of the memory cell MC
16
. The other end of the current path of the select transistor SD
1
is connected to a bit line BL. The other end of the current path of the select transistor SS
1
is connected to a source line SL.
The gate of the select transistor SD
1
is connected to a select line SGD
1
. The gate of the select transistor SS
1
is connected to a select line SGS
1
. Also, the gates of the memory cells MC
1
to MC
16
are connected to word lines WL
1
-
1
to WL
1
-
16
, respectively.
The select line SGD
1
, which controls select transistor SD
1
as it is connected to the bit line BL, is connected to one end of a current path of a transfer transistor MN
1
-
0
. The other end of this current path is connected to a select line control circuit
51
via a select line SGD. Each of the word lines WL
1
-
1
to WL
1
-
16
is connected to one end of a current path of a corresponding one of transfer transistors MN
1
-
1
to MN
1
-
16
. The other end of each of these current paths is connected to a corresponding one of word line control circuits
52
-
1
to
52
-
16
via a corresponding one of control gate lines CG
1
to CG
16
. Furthermore, the select line SGS
1
, which control select transistor SS
1
as it is connected to the source line SL, is connected to one end of a current path of a transfer transistor MN
1
-
17
. The other end of this current path is connected to a select line control circuit
53
via a select line SGS.
The select line control circuit
51
supplies a voltage to the select line SGD. The word line control circuits
52
-
1
to
52
-
16
supply a voltage to the control gate lines CG
1
to CG
16
. The select line control circuit
53
supplies a voltage to the select line SGS.
The gates of the transfer transistors MN
1
-
0
to MN
1
-
17
are connected together to a gate line G
1
, and this gate line G
1
is connected to a high-voltage transfer circuit
54
-
1
. A high voltage generator
55
supplies a voltage equal to or higher than a power supply voltage Vcc to the high-voltage transfer circuit
54
-
1
via a transfer line LPIN. An address signal ADDRESS is

Affiliated with

Also associated with

Rating

Electrically erasable and programmable semiconductor memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electrically erasable and programmable semiconductor memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electrically erasable and programmable semiconductor memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2864292