Electrically erasable and programmable read-only memory having r

Details Electrically erasable and programmable read-only memory having r Electrically erasable and programmable read-only memory having r

1995-04-27

1996-12-17

Zarabian, A.

Static information storage and retrieval

Floating gate

Particular biasing

365200, G11C 700

Patent

active

055860753

ABSTRACT:
A non-volatile semiconductor memory having a redundant memory cell row and a row address selector. During one of read and write operations, the row address selector outputs a regular row address signal from a row address signal buffer as the selected row signal. During an erase operation, the row address selector outputs a defective row address signal from a defective row address memory as the selected row signal, and a row decoder unit provides an erase preventing voltage to one of unused word line and unused redundant word line according to the selected row address signal, a redundant row use flag signal, and a substitution signal to prevent the erasing of unused memory cells.

REFERENCES:
patent: 4630241 (1986-12-01), Kobayashi

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