Electrically erasable and programmable read-only memory cells wi

Details Electrically erasable and programmable read-only memory cells wi Electrically erasable and programmable read-only memory cells wi

1992-11-24

1994-11-22

LaRoche, Eugene R.

Static information storage and retrieval

Floating gate

Particular biasing

437 43, 437 52, G11C 700, H01L 2170

Patent

active

053674839

ABSTRACT:
A method for producing electrically erasable and programmable read-only memory cells with a single polysilicon level, including the use of a sacrificial layer of silicon oxide to produce a high-thickness silicon oxide layer on the active area. The active area of the cell is protected from heavy source and drain implantation in order to improve reliability.

REFERENCES:
patent: 5254489 (1993-10-01), Nakata
Patent Abstracts of Japan, vol. 6, No. 259 (E-149) (1137) Dec. 17, 1982 & JP-A-57155769 (Fujistu K.K.) Sep. 25, 1982.
Patent Abstracts of Japan, vol. 12, No. 403 (E-674) (3250) Oct. 26, 1988 & JP-A-63144559 (Toshiba Corp) Jun. 16, 1988.

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