Electrically erasable and programmable non-volatile storage loca

Details Electrically erasable and programmable non-volatile storage loca Electrically erasable and programmable non-volatile storage loca

1998-01-09

1999-03-16

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518529, 36518533, 365218, G11C 1604

Patent

active

058838325

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

In applications for general control tasks, but in particular in smart cards, microcontrollers require non-volatile memories as program memories and data memories. Particularly when used in battery-operated portable data media, for example in the case of mobile data transmissions and data processing, or with wire-free power supply, for example in the case of contact-free smart cards, only programming and erasing methods having a low power consumption are acceptable, in particular for the data memory. In the same way, the supply voltages should be less than 3 V. Since controllers and smart cards are subjected to high pricing pressures, it is important for widespread use that the production process complexity for the non-volatile memories is low.
The FLOTOX-EEPROM cells which are widely used in smart cards nowadays, as memory! by Dietrich Rhein and Heinz Freitag, Springer Press, Vienna 1992, in particular on page 122, are distinguished by low power consumption since they are programmed and erased via Fowler-Nordheim tunnel currents. In consequence, the programming voltages can also easily be produced on the chip from low supply voltages, which may be less than 3 V. Such memories can be reprogrammed byte by byte so that FLOTOX-EEPROM cells are particularly suitable for data memories which are reprogrammed in operation. These FLOTOX-EEPROM cells comprise a selection transistor and a storage transistor and therefore require a large cell area, so that only small-memories can be implemented on a chip. In addition, as a result of the high required programming voltage of 15 to 20 V, the implementation of the high-voltage transistors to allow this programming voltage to be switched is costly.
In contrast to EEPROMs, flash memories are implemented with-only one transistor per memory cell so that considerably more complex memories than with FLOTOX-EEPROM cells are possible here. However, they are programmed with hot charge carriers (channel hot electron: CHE). This type of programming requires high programming currents, which limit the minimal supply voltage to about 5 V. They cannot therefore be used as data memories, which are intended to be reprogrammed in operation from low supply voltages or via contact-free power supplies. A split-gate flash EEPROM cell which is usual nowadays, is likewise illustrated and described Memories!.
U.S. Pat. No. 5,294,819 also shows a one-transistor EEPROM cell, which is formed with only one MOS transistor, which is formed by a source-channel-drain junction in which there are constructed in a semiconductor substrate of a first conductivity type a drain region and a source region of a second conductivity type and having a polarity opposite to that of the first conductivity type. The cell has a gate electrode which is at a floating potential and is electrically insulated from the drain area by a tunneling oxide and from a channel region, which is located between the drain area and the source area, by a gate oxide, and extends at least over a part of the channel region and a part of the drain region in the source-channel-drain direction, and a control electrode which is electrically insulated from the gate electrode by a coupling oxide.
There, both erasing and programming are carried out by means of tunneling currents, although use is made only of a high positive voltage which is applied either to the control gate or to the drain terminal of the transistor, in order to bring electrons to the control gate or take them away. Owing to the use of only a high positive voltage, the latter must have a large absolute value of approximately 18 volts, resulting in the high outlay for insulation on the semiconductor chip.
Patent Abstracts of Japan, Vol. 15, No. 241 and Japanese reference JP-A-3,074,881 likewise show a non-volatile memory cell having the design described above. There, a negative voltage is applied to the control gate and a low voltage is applied to the drain electrode in order to remove electrodes from the memory gate. However, it is not disclosed how the

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"A 5-V Only 16-Mb Flash Memory With Sector Erase Mode," by Toshikatsu Jinbo et al., IEEE Journal Of Solid State Circuits, vol. 27, No. 11, Nov. 1992, pp. 1547-1553.
"Two-Dimensional Numerical Analysis of Floating-Gate EEPROM Devices" by Ann Concannon et al, IEEE Transactions On Electron Devices, vol. 40, No. 7, Jul. 1993, pp. 1258-1262.

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