Static information storage and retrieval – Floating gate – Particular biasing
Patent
1992-09-21
1994-10-18
LaRoche, Eugene R.
Static information storage and retrieval
Floating gate
Particular biasing
36518905, 365201, G11C 1602
Patent
active
053574621
ABSTRACT:
A NAND-cell type EEPROM includes an array of memory cells connected to bit lines. Each cell includes one transistor with a floating gate and a control gate electrode, wherein electrons are tunneled to or from the floating gate to write a data thereinto. A sense/latch circuit is connected to the bit lines, and selectively performs a sense operation and a latch operation of the write data. A program controller is provided for writing the data into a selected memory cell in a designated area, and for reading the data written in the selected cell to verify whether or not its resultant threshold voltage falls within an allowable range. If it is insufficient, the data is rewritten thereinto. A rewrite-data setting section is provided for performing a logic operation with respect to a read data from the selected cell and the write data being latched in the sense/latch circuit, and for updating automatically a rewrite data being stored in the sense/latch circuit with respect to every bit line in accordance with the actual write state as being verified. The sense/latch circuit includes a CMOS flip-flop circuit, which acts as a data-latch at the beginning of the verify operation, and serves as a sense amplifier once after it is reset.
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Nakamura Hiroshi
Odaira Hideko
Tanaka Tomoharu
Tanaka Yoshiyuki
Kabushiki Kaisha Toshiba
LaRoche Eugene R.
Tran Andrew Q.
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