Electrically erasable and programmable non-volatile semiconducto

Details Electrically erasable and programmable non-volatile semiconducto Electrically erasable and programmable non-volatile semiconducto

1996-11-14

1998-06-16

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518521, 36518517, 36518518, 36518512, G11C 1602

Patent

active

057681902

ABSTRACT:
A NAND-cell type EEPROM having an array of memory cells connected to bit lines. Each cell includes one transistor with floating and control gate electrodes. Electrons are tunneled to or from the floating gate to write data. A sense/latch circuit is connected to the bit lines for selectively performing sense and latch operations of the write data. A program controller is provided for writing and verifying the data into a selected memory cell. Data is rewritten if a resultant threshold voltage in the selected memory cell of the written data is insufficient. A rewrite-data setting section is provided for performing a logic operation with respect to data read from the selected cell and write data being latched into the sense/latch circuit, and for automatically updating a rewrite data being stored in the sense/latch circuit with respect to every bit line in accordance with the memory being verified. The sense/latch circuit includes a CMOS flip-flop circuit, which acts as a data-latch at the beginning of the verify operation, and serves as a sense amplifier after being reset.

REFERENCES:
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5357462 (1994-10-01), Tanaka et al.
patent: 5361227 (1994-11-01), Tanaka et al.
Advanced Micro Devices, Bipolar/MOS Memories Data Book, ISSN 0888-4714, pp. 6-1 through 6-14, 1986.
SEEQ Technology, Inc., SEEQ Data Book 1988/89, pp. 3-1 thru 3-7.

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