Electrically erasable and programmable non-volatile memory devic

Details Electrically erasable and programmable non-volatile memory devic Electrically erasable and programmable non-volatile memory devic

1997-05-08

1999-12-07

Nelms, David

Static information storage and retrieval

Floating gate

Particular connection

36518508, 36518511, 365200, G11C 1606

Patent

active

059994509

ABSTRACT:
An electrically erasable and programmable non-volatile memory device comprises at least one memory sector comprising an array of memory cells arranged in rows and first-level columns, the first-level columns being grouped together in groups of first-level columns each coupled to a respective second-level column, first-level selection means for selectively coupling one first-level column for each group to the respective second-level column, second-level selection means for selecting one of the second-level columns, first direct memory access test means activatable in a first test mode for directly coupling a selected memory cell of the array to a respective output terminal of the memory device, redundancy columns of redundancy memory cells for replacing defective columns of memory cells, and a redundancy control circuit comprising defective-address storage means for storing addresses of the defective columns and activating respective redundancy columns when the defective columns are addressed. The redundancy control circuit comprises second direct memory access test means activatable in a second test mode together with the first direct memory access test means for directly coupling memory elements of the defective-address storage means to respective second-level columns of the array, whereby the memory elements of the defective-address storage means can be directly coupled to output terminals of the memory device.

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