Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-10-26
2002-07-16
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185070, C365S185290, C365S203000, C365S204000
Reexamination Certificate
active
06421273
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to semiconductor devices, and in particular to an electrically erasable and programmable, non-volatile memory device.
For numerous applications, for example for portable data media (chip cards), mobile data processing, wireless data and power transmission, safety equipment, and motor vehicles, it is necessary to store data in such a way that they remain preserved even if the power supply is turned off or fails. For this purpose, one uses not only data storage on magnetic media, which is expensive and requires a large amount of space and energy, but also electrically erasable and programmable, non-volatile semiconductor memories.
As known, there are two primary types of electrically erasable and programmable non-volatile semiconductor memories: (i) EEPROMs (electrically erasable and programmable read-only memories) and (ii) flash EPROMs (sometimes also called flash EEPROMs). EEPROMs use the well-known Fowler-Nordheim tunnel effect to erase and to program, while flash EPROMs use hot electron injection to erase the Fowler-Nordheim tunnel effect. As a rule, they share the feature of having at least two transistors, one of which has a floating gate. The floating gate is coupled to a tunnel diode arrangement, to charge the associated transistor as needed. Furthermore, at least one other transistor is used to activate or select the cell.
However, both EEPROMs and flash EPROMs take a relatively long time to program. In addition, they permit only a limited number of programming processes, and they are more prone to break down than other semiconductor memories. Consequently, EEPROMs and flash EPROMs have only restricted applicability for safety applications.
Therefore, there is a need for an electrically erasable and programmable non-volatile memory device that does not have these disadvantages.
SUMMARY OF THE INVENTION
Briefly, according to an aspect of the present invention, an electrically erasable and programmable non-volatile memory device includes a first electrically erasable and programmable non-volatile memory cell, which has a bit line, a selection line, a programming line, and an erase line. The memory device also includes a bistable flip-flop with two mutually inverted status lines, one of which is connected to the bit line of the memory cell, while the other one is connected to the programming line of the memory cell. The memory device further includes a switching device, connected to the flip-flop, to connect at least one data input line to one of the status lines of the flip-flop, in dependence on a switching signal.
A feature of the inventive memory device is that its outputs are valid constantly and without significant delay, because these outputs receive the data before the device is actually programmed, so that their effects on other circuit components can be tested before the actual programming process, and these components can be modified as necessary, already before programming. This avoids unnecessary reprogramming and thus an unnecessary shortening of the lifetime of the memory device.
To charge the memory device, the data input line(s) is/are connected to the bit line(s), and the flip-flop is supplied with a low voltage. For erasing the memory device, the flip-flop is supplied with a higher voltage, and the erase line of the memory cell is driven with the higher voltage. For programming the memory device, the flip-flop is supplied with the higher voltage. Finally, for reading the memory device, the flip-flop is supplied with the low voltage, and the selection line of the memory cell is driven with the low voltage.
In a preferred embodiment, a second electrically erasable and programmable non-volatile memory cell is present. The bit line and the erase line of the second memory cell are connected to the bit line and the erase line of the first memory cell, respectively. The selection line of the second memory cell is driven like the first memory cell to charge, erase, program, and read the memory device. The second memory cell increases redundancy and consequently improves the entire device's security against breakdown of one memory cell.
In yet another embodiment, at least one other electrically erasable and programmable non-volatile memory cell is present. The bit line and the erase line of the other memory cell(s) are coupled to the erase line (ER) and the bit line of the first memory cell, respectively, in such a way that when the memory device is being charged or read, the drive of the other memory cell(s) is the same as the respective drive of the first memory cell, and while the memory device is being erased and programmed, the drive of the other memory cell(s) is the same as the drive of the first memory cell. This feature further increases redundancy and thus improves security, since a systematic error on both sides of the bistable flip-flop can be detected and eliminated through the inverse drive of at least one other memory cell. To check the states of the individual memory cells, the selection lines of the memory cells preferably are also driven individually.
To test the memory device with an appropriate switching signal, for example by appropriately actuating the data input lines, all the memory cells can be brought to the same state, and then read out individually. The functionality of each memory cell, before and after erasing and/or programming, can thus be determined. For programming, the selection line(s) of the memory cell(s) preferably are not actuated in this case.
A switching device may switch the data input lines to the status lines of the flip-flop, which assumes a high-ohm state in the absence of a switching signal. Such switching devices thus can have, for example, a tri-state output. A controllable switch for data lines can thus be realized without great complication.
In a preferred design of the inventive memory arrangement at least one memory cell has a floating gate transistor, whose source connection is connected to a reference point, whose drain connection is connected to the bit line via the controlled section of a selection transistor, and whose gate connection is coupled, on the one hand, via a tunnel capacitance to the erase line and, on the other hand, via the gate source section of an injector transistor to the programming line. Advantageously, this inexpensively creates a reliable flash EPROM cell.
The bistable flip-flop and the memory cell(s) may have a common reference point. Here, as also in other design forms, the reference point can be shifted for erasing and programming to protect other circuit components. This arrangement preferably has an output circuit, which is connected to at least one status line of the flip-flop, and whose cross current does not rise significantly when the reference point rises.
Accordingly, a switching device can also be present, to connect the data input line(s) to the status line(s) of the flip-flop, to change the level and/or to adapt the reference point, and to compensate the rise of the reference point in view of the data input lines.
These and other objects, features and advantages of the present invention will become more apparent in light of the following detailed description of preferred embodiments thereof, as illustrated in the accompanying drawings.
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Micronas GmbH
Nguyen Viet Q.
Samuels , Gauthier & Stevens, LLP
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