Electrically erasable and programmable memory comprising an...

Details Electrically erasable and programmable memory comprising an... Electrically erasable and programmable memory comprising an...

2003-04-22

2004-12-07

Lam, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S189110, C365S175000

Reexamination Certificate

active

06829169

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an electrically programmable and erasable memory comprising a memory array of memory cells, and a distribution line of an internal supply voltage linked to a receiving terminal of an external supply voltage and to a booster circuit. The present invention relates more particularly to the management of the internal supply voltage of this memory, particularly during phases of reading memory cells.
BACKGROUND OF THE INVENTION
An example of the architecture of an electrically erasable and programmable memory is schematically represented in FIG.
1
A. The illustrated memory MEM
1
comprises a memory array MA in which memory cells C
i,j,k
are linked to word lines WL
i
and to bit lines BL
j,k
arranged in columns, wherein i is a word line index, k is a column index, and j is a bit line index within a column.
Each memory cell C
i,j,k
comprises a floating-gate transistor FGT, the drain of which is linked to a bit line BL
j,k
through an access transistor AT. The gate of the transistor FGT is linked to a gate control line CGL
k
through a gate control transistor CGT
i,k
. The gate of the gate control transistor CGT
i,k
and the gate of the access transistor AT are connected to a word line WLi.
To ensure access to the memory cells for reading and writing, the memory also comprises a line decoder RDEC, a column decoder CDEC, a column lock circuit CLC, a column selection circuit CSC, a programming circuit PLC and a read circuit SA.
The read circuit SA comprises sense amplifiers, such as eight amplifiers SA
0
to SA
7
, for example, if the memory array is made up of eight-bit words. Each amplifier SA
j
of rank j is linked, through a multiplexing bus MB, to each bit line BL
j,k
of the same rank j present in each column of the memory array.
The line decoder RDEC and the column decoder CDEC respectively receive the most significant bits and the least significant bits of an address AD, and respectively deliver I line selection signals RS
i
and K column selection signals CS
k
. After application of an address AD, a line selection signal RS
i
out of the I signals RS
i
is set to 1 by the line decoder, while the other signals RS
i
are equal to 0. Similarly, a column selection signal CS
k
out of the K signals CS
k
is set to 1 by the column decoder while the other signals CS
k
are equal to 0.
From an electrical point of view, a line selection signal RS
i
equal to 1 has a voltage level equal to an internal supply voltage Vps applied to a supply terminal T
1
of the decoder RDEC. Similarly, a selection signal CS
k
equal to 1 has a voltage level equal to an external supply voltage Vcc applied to a supply terminal T
2
of the decoder CDEC.
The column selection circuit CSC comprises bit line selection transistors ST
j,k
. Each transistor ST
j,k
is arranged in series on a bit line BL
j,k
and allows the bit line to be connected to a sense amplifier SA
j
. The transistors ST
j,k
present on bit lines of the same column are driven by the selection signal CS
k
of the column considered.
The column lock circuit CLC comprises column selection locks CL
k
and receives a gate control voltage Vcg at an input terminal. Each lock CL
k
is activated by a column selection signal CS
k
. Each lock delivers the voltage Vcg to the gate control line CGL
k
of the column to which it is assigned, when it is activated by the corresponding signal CS
k
.
The voltage Vps electrically supplies the column selection locks CL
k
and is applied for this purpose to a supply terminal T3 of the circuit CLC. The programming circuit PLC comprises programming locks PL
j,k
each having an output linked to a bit line BL
j,k
. The locks PL
j,k
are activated by the selection signals CS
k
to load data [DATA] to be programmed, on the basis of one bit per lock, upon reception of a signal LOAD.
The voltage Vps electrically supplies the programming locks PL
j,k
and is applied for this purpose to a supply terminal T
4
of the circuit PLC. The voltage Vps is delivered by a distribution line
10
represented in
FIG. 1B
, connected to the terminals T
1
, T
3
, T
4
of the elements described above. The distribution line
10
is linked to a supply terminal
11
of the memory through a switch transistor Tsw that is off (transistor on) during the column selection, programming lock loading and read periods. The voltage Vps is then substantially equal to the voltage Vcc, disregarding the voltage drop in the transistor Tsw.
The distribution line
10
is also linked to the output of a booster circuit PMP
1
, generally a charge pump, supplied by the voltage Vcc and controlled by a regulator REG
1
. During phases of erasing and programming memory cells, the switch Tsw is on (transistor blocked) and the charge pump is activated. The charge pump delivers a high voltage Vpp, on the order of 15 to 20 V, that is gradually applied to the line
10
by a ramp generator RAMPGEN comprising a PMOS transistor arranged in series on the line
10
. This transistor is represented with dotted lines, as it is transparent from an electrical point of view (it leads to hardly any voltage drop in the line
10
) except during the ramp generation periods.
The gate control voltage Vcg is delivered by a circuit CGGEN supplied by the voltage Vps. When the memory is in the read phase and the voltage Vps is equal to Vcc (Tsw on), the voltage Vcg delivered by the circuit CGGEN is equal to a read voltage Vread. When the memory is in the erase phase and the voltage Vps is equal to the high voltage Vpp, the voltage Vcg delivered by the circuit CGGEN is equal to a high erase voltage Verase. Finally, when the memory is in the programming phase and the voltage Vps is equal to the high voltage Vpp, the voltage Vcg delivered by the circuit CGGEN is equal to 0 (ground).
Such a memory is generally required to have technical specifications that are quite wide and fairly unrestrictive for the user as far as the external supply voltage Vcc is concerned, with a tolerance range from 1.6 V to 5.6 V, for example. However, in practice, it emerges that a drop in the voltage Vcc in the lowest values of the tolerance range is capable of leading to a malfunction of the memory during periods of reading memory cells.
For a better understanding, it will be assumed, with reference to
FIG. 1A
, that a memory cell C
i,j,k
must be read by an amplifier SAj. A column selection lock CL
k
applies the voltage Vcg to the gate control line CGL
k
. The voltage Vcg is, in this case, equal to Vread and must be found, without attenuation, on the gate of the floating-gate transistor FGT, through the transistor CGT
i,k
. The voltage Vread is between the threshold voltage of the erased transistor and the threshold voltage of the programmed transistor, and enables the sense amplifier SA
j
to find out whether the transistor is on (transistor erased, corresponding to the reading of a 1) or blocked (transistor programmed, corresponding to the reading of a 0). It will be assumed that the voltage Vread is on the order of 1.2 V, as is generally the case, and that the tolerance range for the voltage Vcc is 1.6-5.6 V.
So that the voltage Vread reaches, without attenuation, the control gate of the transistor FGT, the gate of the transistor CGT
i,k
must receive a selection signal RS
i
having a voltage level at least equal to Vread+Vt, wherein Vt is the threshold voltage of the transistor CGT
i,k
. Since the voltage level of a selection signal RS
i
set to 1 is equal to the voltage Vps applied to the supply terminal T
1
of the decoder RDEC, the voltage Vps must be higher or equal to a threshold Vmin1 such that:
Vmin
1=
Vread+Vt,
i.e., approximately 2.2 V in the abovementioned example. Yet, the threshold Vmin1 is above the lowest values of the voltage Vps contained in the abovementioned tolerance range.
A similar problem is encountered on the bit line BL
j,k
during the reading of the cell. The sense amplifier SA
j
applies a voltage Vpol to the bit line BL
j,k
that must be found on the drain of the transistor FGT after passing through a

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