Electrically enhanced power quad flat pack arrangement

Details Electrically enhanced power quad flat pack arrangement Electrically enhanced power quad flat pack arrangement

1997-04-28

1998-09-01

Picardat, Kevin

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Metallic housing or support

438111, 438124, H01L 2144

Patent

active

058009582

ABSTRACT:
A quad flat pack arrangement which provides for an electrically enhanced integrated-circuit package structure is disclosed. An integrated-circuit die is centrally attached to the top surface of a thermally-conductive, and electrically conductive or insulated substrate. A lead frame having a plurality of inwardly-extending bonding fingers has the bottom sides thereof attached to the top surface of the substrate by a non-conductive adhesive so that an open portion thereof overlies the integrated-circuit die. The plurality of bonding fingers are disposed so as to peripherally surround the integrated-circuit die. A double-sided printed circuit board having first and second conductive layers disposed on its opposite sides is disposed over and bonded to the lead frame. Bonding wires are used to interconnect bonding pads on the integrated-circuit die to the first and second conductive layers. A plastic material is molded around the substrate, die, lead frame, printed circuit board and conductive layers.

REFERENCES:
patent: 5382546 (1995-01-01), Yamada et al.
patent: 5474957 (1995-12-01), Urushima
patent: 5480841 (1996-01-01), Bickford et al.
patent: 5518957 (1996-05-01), Kim

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