Electrically configurable integrated circuit configuration using

Details Electrically configurable integrated circuit configuration using Electrically configurable integrated circuit configuration using

1995-06-07

1996-09-24

Fears, Terrell W.

Static information storage and retrieval

Addressing

Sync/clocking

36523001, G11C 1300

Patent

active

055597513

ABSTRACT:
A programming system for programming an electrically programmable gate array (EPGA) provides a clocked data signal with data cycles of the form 01DD, where the 01 ensures a clock transition each data cycle and the DD constitutes two bit periods with the same data value. The timing is led by a timing sequence of the form 0100. The EPGA measures the period of the timing sequence. For each data cycle, the EPGA detects the 01 transition, then, after a delay equal to twice the measured timing sequence period, generates a clock pulse. The series of clock pulses so generated constitutes a configuration clock. The configuration clock is used to time sampling of the clocked data signal to extract a configuration data signal. The configuration clock and the configuration data signal are used in a conventional manner to program configuration EPROMs of the EPGA.

REFERENCES:
patent: 5483496 (1996-01-01), Murakawa
patent: 5497355 (1996-03-01), Mill et al.
The Programmable Logic Data Book (1994), Xilinx, Inc., San Jose, CA, pp. 196-208.

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