Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1998-10-22
2001-06-19
Paladini, Albert W. (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S261000, C438S017000
Reexamination Certificate
active
06248962
ABSTRACT:
TECHNICAL FIELD
This invention relates to semiconductor processing methods of forming an electrically conductive projection outwardly extending from a substrate, to semiconductor processing methods of providing an electrical interconnection between adjacent different elevation areas on a substrate, and to electrically conductive apparatus. This invention also relates to methods for testing semiconductor circuitry for operability, and to constructions and methods of testing apparatus for operability of semiconductor circuitry.
BACKGROUND OF THE INVENTION
This invention relates to subject matter of our U.S. patent application Ser. No. 08/116,394, filed on Sep. 3, 1993, and entitled “Method and Apparatus for Testing Semiconductor Circuitry for Operability and Method of Forming Apparatus for Testing Semiconductor Circuitry for Operability”, which is now U.S. Pat. No. 5,326,426. This '394 application and patent is hereby fully incorporated into this document by reference.
Aspects of the related disclosure grew out of the needs and problems associated with multichip modules. Considerable advancement has occurred in the last fifty years in electronic development and packaging. Integrated circuit density has and continues to increase at a significant rate. However by the 1980's, the increase in density in integrated circuitry was not being matched with a corresponding increase in density of the interconnecting circuitry external of circuitry formed within a chip. Many new packaging technologies have emerged, including that of “multichip module” technology.
In many cases, multichip modules can be fabricated faster and more cheaply than by designing new substrate integrated circuitry. Multichip module technology is advantageous because of the density increase. With increased density comes equivalent improvements in a signal propagation speed and overall device weight unmatched by other means. Current multichip module construction typically consists of a printed circuit board substrate to which a series of integrated circuit components are directly adhered.
Many semiconductor chip fabrication methods package individual dies in a protecting, encapsulating material. Electrical connections are made by wire bond or tape to external pin leads adapted for plugging into sockets on a circuit board. However, with multichip module constructions, non-encapsulated chips or dies are secured to a substrate, typically using adhesive, and have outwardly exposed bonding pads. Wire or other bonding is then made between the bonding pads on the unpackaged chips and electrical leads on the substrate.
Much of the integrity/reliability testing of multichip module dies is not conducted until the chip is substantially complete in its construction. Considerable reliability testing must be conducted prior to shipment. In one aspect, existing technology provides temporary wire bonds to the wire pads on the die for performing the various required tests. However this is a low-volume operation, and further requires the test bond wire to ultimately be removed. This can lead to irreparable damage, thus effectively destroying the chip.
Another prior art test technique uses a series of pointed probes which are aligned to physically engage the various bonding pads on a chip. One probe is provided for engaging each bonding pad for providing a desired electrical connection. One drawback with such testing is that the pins undesirably on occasion penetrate completely through the bonding pads, or scratch the bonding pads possibly leading to chip ruin.
The invention described below was motivated in the desire to develop improved electrical interconnection techniques associated with the invention of the related '394 application. It is, however, recognized that the invention disclosed herein is further applicable to methods and constructions beyond that disclosed in the related '394 disclosure. This invention, therefore, is limited only by the accompanying claims appropriately interpreted in accordance with the Doctrine of Equivalents.
REFERENCES:
patent: 3412456 (1968-11-01), Ebisawa
patent: 3469019 (1969-09-01), Reimann
patent: 4105970 (1978-08-01), Katz
patent: 4141055 (1979-02-01), Berry et al.
patent: 4182781 (1980-01-01), Hooper et al.
patent: 4189825 (1980-02-01), Robillard et al.
patent: 4312117 (1982-01-01), Robillard et al.
patent: 4315984 (1982-02-01), Okazaki et al.
patent: 4417206 (1983-11-01), Stowers
patent: 4499656 (1985-02-01), Fabian et al.
patent: 4585991 (1986-04-01), Reid et al.
patent: 4881118 (1989-11-01), Niwayama et al.
patent: 4924589 (1990-05-01), Leedy
patent: 4929999 (1990-05-01), Hoeberechts et al.
patent: 4937653 (1990-06-01), Blonder et al.
patent: 4952272 (1990-08-01), Okino et al.
patent: 4963225 (1990-10-01), Lehman-Lamar
patent: 5014161 (1991-05-01), Lee et al.
patent: 5032541 (1991-07-01), Sakamoto et al.
patent: 5045780 (1991-09-01), Swart
patent: 5072116 (1991-12-01), Kawade et al.
patent: 5103557 (1992-04-01), Leedy
patent: 5137461 (1992-08-01), Bindra et al.
patent: 5177438 (1993-01-01), Littlebury et al.
patent: 5177439 (1993-01-01), Liu et al.
patent: 5196251 (1993-03-01), Bakhura et al.
patent: 5206585 (1993-04-01), Chang et al.
patent: 5235140 (1993-08-01), Reele et al.
patent: 5239260 (1993-08-01), Widder et al.
patent: 5245135 (1993-09-01), Schreiber et al.
patent: 5262718 (1993-11-01), Svendsen et al.
patent: 5307561 (1994-05-01), Feigenbaum et al.
patent: 5323035 (1994-06-01), Leedy
patent: 5326428 (1994-07-01), Farnworth et al.
patent: 5334804 (1994-08-01), Love et al.
patent: 5353195 (1994-10-01), Fillion et al.
patent: 5367253 (1994-11-01), Wood et al.
patent: 5402077 (1995-03-01), Agahdel et al.
patent: 5419807 (1995-05-01), Akram et al.
patent: 5420520 (1995-05-01), Anschel et al.
patent: 5431328 (1995-07-01), Change et al.
patent: 5468917 (1995-11-01), Brodsky et al.
patent: 5471151 (1995-11-01), DiFrancesco
patent: 5477087 (1995-12-01), Kawakita et al.
patent: 5478779 (1995-12-01), Akram
patent: 5523697 (1996-06-01), Farnworth et al.
patent: 5541525 (1996-07-01), Wood et al.
patent: 5559444 (1996-09-01), Farnworth et al.
patent: 5625297 (1997-04-01), Arnaudov et al.
patent: 5716218 (1998-02-01), Farnworth et al.
patent: 5790377 (1998-08-01), Schreiber et al.
patent: 5831832 (1998-11-01), Gillette et al.
patent: 5869787 (1999-02-01), Akram
patent: 329314 (1989-08-01), None
patent: 57-14838 (1982-09-01), None
patent: 2-5540 (1990-01-01), None
patent: 2232946 (1990-09-01), None
patent: 53171 (1991-03-01), None
patent: 108350 (1991-05-01), None
patent: 410446 (1992-01-01), None
Moto's Nakano, “A Probe for Testing Semiconductor Integrated Circuits and a Test Method Using said Probe,” Mar. 25, 1991, Japanese Patent Office Disclosure No. Hei 3-69131, filing No. Hei 1-0205301, filing date Aug. 8, 1989.
Cuneo Kamand
Micro)n Technology, Inc.
Paladini Albert W.
Wells, St. John, Roberts Gregory & Matkin P.S.
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