Electrically alterable, nonvolatile floating gate memory device

Details Electrically alterable, nonvolatile floating gate memory device Electrically alterable, nonvolatile floating gate memory device

1982-12-10

1985-04-23

Moffitt, James W.

Static information storage and retrieval

Floating gate

Particular biasing

357 235, G11C 1140

Patent

active

045133972

ABSTRACT:
An electrically alterable, nonvolatile floating gate memory device is described wherein the floating gate is a second level polysilicon layer. The first level polysilicon layer is provided with an aperture in order for only a small portion of the second level polysilicon floating gate to extend through the aperture for coupling to the substrate. Chip area is conserved by coupling the floating gate to the substrate at the portion of the channel region that conduction takes place by means of the self aligned aperture.

REFERENCES:
patent: 3500142 (1970-03-01), Kahng
patent: 3660819 (1972-05-01), Frohman-Bentchkowski
patent: 4328565 (1982-05-01), Harari
patent: 4355375 (1982-10-01), Arakawa
patent: 4417264 (1983-11-01), Angle
"16-K EE-PROM Relies on Tunneling for Byte-Erasable Program Storage", W. S. Johnson, et al., Electronics, Feb. 28, 1980, pp. 113-117.
IBM Technical Disclosure Bulletin-vol. 23, No. 2, Jul. 1980; pp. 543-545.

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