Electrically alterable floating gate semiconductor memory device

Details Electrically alterable floating gate semiconductor memory device Electrically alterable floating gate semiconductor memory device

1976-12-27

1978-09-05

Hecker, Stuart N.

Static information storage and retrieval

Floating gate

Particular biasing

357 23, G11C 1140

Patent

active

041125096

ABSTRACT:
An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates which are interposed between the gate oxide and control gates formed by row address lines. The cells may be electrically erased by applying selected voltages to the source, drain, control gate and substrate; the floating gate discharges through the insulator between the floating gate and the control gate, i.e., between first and second level polysilicon.

REFERENCES:
patent: 3760378 (1973-09-01), Burns
patent: 3836992 (1974-09-01), Abbas et al.
patent: 3984822 (1976-10-01), Simko et al.
Chang, Nonvolatile Semiconductor Memory Devices, Proceedings of the IEEE, vol. 64, No. 7, 7/76, pp. 1039-1059.
Iizuka, et al., Electrically Alterable Avalanche-Injection-Type MOS Read Only Memory with Stacked-Gate Structure, IEEE, Trans. on Electron Dev., 4/76, pp. 379-387.
Terman, Floating Avalanche-Injection Metal-Oxide Semiconductor Device with Low-Write Voltage, IBM Tech. Disclosure Bul. vol. 14, No. 12, 5/72, p. 3721.

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