Electrically alterable floating gate memory with self-aligned lo

Details Electrically alterable floating gate memory with self-aligned lo Electrically alterable floating gate memory with self-aligned lo

1978-05-26

1981-03-24

Wojciechowicz, Edward J.

357 45, 357 46, 357 50, 357 51, 357 59, 357 91, H01L 2702

Patent

active

042583780

ABSTRACT:
An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates, and electrically erased power voltages applied to the source, drain, control gate and substrate. The floating gate discharges through the insulator between the floating gate and the control gate, i.e., between first and second level polysilicon. An enhancement mode transistor in series with the floating gate device in each cell provides an improved voltage window for deprogramming by allowing the transistor created by the floating gate to go into the depletion mode. The threshold of this series enhancement transistor is lowered by an implant step in the process which is self-aligning.

REFERENCES:
patent: 4084108 (1978-04-01), Fujimoto
patent: 4119995 (1978-10-01), Simko

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