Electrical through wafer interconnects

Details Electrical through wafer interconnects Electrical through wafer interconnects

2003-01-22

2004-12-28

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

Reexamination Certificate

active

06836020

ABSTRACT:

BRIEF DESCRIPTION OF THE INVENTION
This invention relates generally to electrical through wafer interconnects and more particularly to through wafer interconnects in which the parasitic capacitance is minimized.
BACKGROUND OF THE INVENTION
In co-pending application Ser. No. 09/667,203 filed Sep. 21, 2000, there is described an ultrasonic transducer with through wafer connections. Capacitive micro machined ultrasonic transducer arrays include membranes which are supported on the front side of a substrate or wafer by isolator supports such as silicon nitride, silicon oxide and polyimide. Transducers of this type are described, for example, in U.S. Pat. Nos. 5,619,476; 5,870,351; and 5,894,452. Micromachined two-dimensional arrays of droplet ejectors which include a flexible membrane supported on a substrate are described, for example, in U.S. Pat. No. 6,474,786. Other two-dimensional device arrays such as for example, arrays of vertical cavity surface emitting lasers, mirrors, piezoelectric transducers, photo detectors and light emitting diodes are formed on and supported by the front side of wafers or substrates.
One of the main problems in fabricating two dimensional arrays is that of addressing the individual array elements. If the array size is large, a significant sacrifice in the array element area is required if the addressing is done through a routing network on the top side of the substrate. The interconnect between the array elements and their electronics gives rise to parasitic capacitance which limits the dynamic range and frequency bandwidth of the device array. It is therefore advantageous to have the electronic circuitry as close to the array elements as possible. However, integrating the devices, the electronics and the interconnects on the same wafer leads to a compromise in the performance of both the electronics and the device array.
An excellent solution to the problem is to fabricate separately the optimum device array and the electronics, provide through wafer interconnects with high aspect ratio and the flip chip bond the wafer to the electronics. This also provides a lower parasitic capacitance between the electronic circuit and the array elements. However it is desirable to further reduce the parasitic capacitance.
OBJECTS AND SUMMARY OF THE INVENTION
In accordance with the invention, the reduction in parasitic capacitance is achieved by employing reverse biased pn, Schottky junctions, or MIS (Metal Insulator Semiconductor) biasing to depletion in the interconnects.
It is an object of the present invention to provide a wafer with through wafer interconnects with a low parasitic capacitance and resistance.
It is a further object of the present invention to provide a wafer which includes front side and back side pads and a through wafer interconnect with low parasitic capacitance and resistance.
There is provided a wafer with through wafer interconnect. The wafer included spaced through wafer vias which extend between the back side and front side of the wafer, a conductor within each of the vias connected to front and back side pads and means associated with said conductor and pads and the wafer for providing a depletion region in the wafer between the conductor and pads.


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