Electrical signal noise suppressing apparatus

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

235183, 328127, 340347NT, G06G 712, G06G 718

Patent

active

039783480

ABSTRACT:
A integrator circuit is calibrated prior to measuring input signals therewith, by applying a reference voltage thereto with the output thereof applied to a comparator which has an output threshold set by a limit value signal proportional to the reference voltage. Clock pulses are accumulated by a counter until the comparator output threshold is reached and then a synchronizing means is actuated to simultaneously disconnect the reference voltage from the integrator and stop the counter, to reset the integrator, and to simultaneously connect the input signal to the integrator and the clock pulses to count down the accumulated count in the counter which thereby initiates the measuring mode. When the counter reaches zero, an output signal is produced which disconnects the input signal from the integrator to thereby stop the measuring mode. A frequency divider may be included to adjust the down counting frequency so that the integrating period of the measuring mode can be adjusted in proportion to the constant of integration that existed during the calibration mode.

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patent: 3577140 (1971-05-01), Aasnaes
patent: 3617885 (1971-11-01), Wheable
patent: 3623073 (1971-11-01), Wheable
patent: 3649826 (1972-03-01), Larsson et al.
patent: 3716849 (1973-02-01), Metcalf
patent: 3729733 (1973-04-01), Dorey
patent: 3765012 (1973-10-01), Grutzediek et al.
patent: 3826983 (1974-07-01), Garratt et al.
patent: 3842416 (1974-10-01), Eto
patent: 3849775 (1974-11-01), Buchanan et al.

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