Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2006-05-23
2006-05-23
Geyer, Scott (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Reexamination Certificate
active
07049171
ABSTRACT:
An electronic package is provided having a connector and a solder joint that is less susceptible to thermal fatigue. The package includes a die including a first electrically conductive connecting surface having a first coefficient of thermal expansion and a substrate including electrical circuitry and a second electrically conductive connecting surface having a second coefficient of thermal expansion. The package further includes a solder joint connecting the first connecting surface to the second connecting surface. One of the first and second connecting surfaces includes a plurality of pads spaced from each other. By employing an electrical connection having a plurality of pads spaced from each other, the solder joint is relieved to reduce fatigue caused by thermal cycling.
REFERENCES:
patent: 5081520 (1992-01-01), Yoshii et al.
patent: 5523620 (1996-06-01), Eytcheson et al.
patent: 5930601 (1999-07-01), Cannizzaro et al.
patent: 6054765 (2000-04-01), Eytcheson et al.
patent: 6436730 (2002-08-01), Melton et al.
patent: 6566164 (2003-05-01), Glenn et al.
patent: 2003/0113954 (2003-06-01), Glenn et al.
Chmielewski Stefan V.
Delphi Technologies Inc.
Geyer Scott
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